Mains setpoint monitoring basic circuit: best choice.

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So the divider is VRef= Vmains_rectfd*(R3+5k)/((R3+5k)+(R7+R2)) I believe.
The divider voltage is the main's rectified average voltage, not the mains rectified voltage.
I think you meant that Vmains_rectfd = 0.5*((Vac*1.414) - 2*Vd)*2/pi.
Yes.
Also, how does R_Hyst affect hysteresis? It affects it as a lonely component or with another component?
It adds a small amount of positive feedback to the Ref node.
The amount of feedback is determined by the voltage divider between R_Hyst and the equivalent resistance at the Ref node.

I just noticed an error in the U3 pot connection.
Attached is the corrected schematic.

 
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