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In Design Flow,
1.During Fix Time Itself,Start ur Area Optimization... “run gate trim”
2.Floorplan: Place macros as close as Possible.. Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the memory, if the pins are one-sided, there-by area could be reduced.
3.During Placement:
Area optimization: An optimization method that optimizes the cell area requirements of the nontiming-critical paths in the design, while increasing the slack of paths that are timing critical.
Trimming is 1st stage of Area Optimization... Bufferin is the 2nd stage of area opti..
In magma Commands are there, For Trimmin,Bufferin.... Try this...
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