lzss Decompression verilog synthesizeable RTL

[sham1810]

Hi,

I am currently writing a decompression engine for lzss in verilog. I need it be fast and need a minimum throughput of 4bytes/cycle. I am currently reading in 4bytes of input data every cycle and then decode the input data to figure out if its a pointer or a literal. If a literal i write it into output FIFO and if its a pointer i push the length and offset in another FIFO(this one is simple synchronous FIFO). I am also designing the output FIFO to have dual reading and writing ports. However i am still not able to meet minimum throughput. Any suggestions on how can i achieve minimum throughput?

 

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Pipeline the design.

 

[sham1810]

Pipeline the design.

My initial thoughts were to pipeline the design but since decompression does not perform any operation on the data it doesn't make sense to pipeline it. It you go through through the decompression algorithm you'll know that it involves a lot of copy pasting data already being written in the output memory. I am planning to use 4 banks for the memory so that i have a way of writing 4bytes/cycle. Any better way you can think of?