LVS using standard cells

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Hi all.

I am trying to do LVS using std. cells from foundry. I am using Cadence tools with Calibre LVS. I am currently using an inverter (with input and output pins) as a test case.

1. Anyone know how to handle inherited gnd/vdd in layout? I see them in the schematic netlist, but I dont know how to include them in the layout. Are there any settings I can set in Calibre LVS.

2. So far I have only achieved to perform LVS by blackboxing the standard cell. I am aware of that this only checks the connections/routing between the standard cells and it does not check the layers inside the standard cell. (I am referring to the Metal1 routes in the standard cell)

I would like to be able to check the routing layers in the standard cell as well. When I run Hierarchical LVS (.gds exported from layout) I get the following errors:

"Nothing in layout"
"Corresponding cells could not be identified"
"Nothing in layout"

I used CALIBRE DESIGNrev and verified that the exported .gds file has all the cells and layers.

Can anyone point me in the right direction?

Thanks in advance.
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