[SOLVED] LVS process in Calibre.

[MANOJKUMARPALO]

Hi ,

I am working on ICC for Layout verification and using Calibre for LVS check.
As per my knowledge,in LVS ,2 netlists are getting compared.
But ,in Synopsis ICC ,it is not the exact,what i know.
There is no role of schematic netlist over here.
Then, how it works?

From some of my seniors ,i got to know that ,the 2 netlists as input to calibre for LVS comparision are getting generated from the layout itself.
Then, how it is getting information about schematic?
I am searching the result for so many days ,but didn't find the correct one.
Please suggest me the correct answer.

Thanks and Regards
Manoj

 

[kumar_eee]

Hi Manoj,
Calibre needs Layout ( in GDS format ) & Source ( Verilog netlist ), which are dumped from the Implementation tools. Later, Verilog Netlist is converted into SPICE format ( CDL ).

Now the calibre has GDS & CDL, it starts comparing the connectivity based on the Rules defined in the Rule Deck ( From Foundry ).

Coming to ICC, This also has the same inputs, but works on the Metal Layers only. We load MilkyWay libraries while starting the PD. This is to reduce the infrastructure & memory requirements.

To Answer you precisely, ICC has the logical connectivity info in the form of verilog netlist. The same can be used or converted in the form of schematic, which is done internally.

 

[MANOJKUMARPALO]

Hi kumar,

thanks for such valuable information's.

But ,i have some doubts......
Please guide me.

1)From the above explanation,do u mean to say ,while we are copying the gds from central database to our local database for modification,the verilog netlist of
schematic for the same gds is getting copied to our local area ? or any kind of linking happens to central area for schematic netlist?

I mean to ask,from where calibre gets the verilog netlist?from local area or central area?

2)If this LVS checking happens for metal layers only,then how calibre works for base layer open and shorts?

Thanks and Regards
Manoj

 

[kumar_eee]

Hi Manoj,
I didn't get your 1st question. What do mean by Local area & Central Area?

1) After dumping the GDS from Implementation tool, the Physical Verification Engineer will merge all the std cell, Macro & TOP level GDS. This gives you the complete GDS ( Contains all the layers including Base). Its your duty to specify the inputs to the Calibre. My assumption is that you will pick the rule files from Central area & design files from your design area.

2) When you perform LVS with Calibre, then the full GDS ( With Base layers ) comes into picture.

Thats the reason why Calibre is being a Sign-off Tool.

 

[MANOJKUMARPALO]

Hi kumar,

Local area is our working area.
Central area is the place ,where the original database is kept.

Now i am clear about gds concept.

As per my knowledge,when we want to make some modification in the original cell,we copy the cell to our local work area ,do modifications.

During this copying process,are we getting a copy of the verilog netlist for that cell in our working area?


That's what ,my 1st question is all about.

From where Calibre gets the verilog netlist?
From central area by means of some linking pointer or from our working area?

Thanks and Regards
Manoj

 

[kumar_eee]

Hi Manoj,
In industry, Central area means where all the libraries ( Std cell, IO, Analog Macro & Memories) are kept ( which is read-only files, only the CAD team will have permission to update).

Local area means where you're executing the design. I guess all your files like GDS,verilog, DEF ...etc will be dumped in your local area.

When you run LVS, you should include CDL libraries of Std cell, Macro.. etc in your Calibre run set file.

You've to convert the Design Verilog netlist into CDL (spice) format, which can be done through V2LVS utility from Calibre.

I hope its clear now.

 

[MANOJKUMARPALO]

Hi Kumar,

Thank you so much for nice explanation.i am clear upto this.

Some more doubts are there.

1)We are giving .gds file as one of the input to calibre,which is a binary file.
Then, how a binary file is getting compared with a spice netlist?

For comparision ,there should be 2 files of same format. right?

2)There are 2 steps for LVS. extraction and comparision

can u please explain me ,what is exactly happening in each step?

Thanks in adavance
Regards
Manoj

 

[kumar_eee]

Manoj,
Calibre is capable of reading the GDS files.

I would suggest you to read the Calibre user Manual to understand more about the LVS & its flow.

 

[MANOJKUMARPALO]

Hi Kumar,

Thanks a lot again......

 

[MANOJKUMARPALO]

Hi kumar,

Some doubts regarding ECO implementation.

When we are implementing any ECO's in our layout i.e buffer insertion,upsizing etc..,it is not showing any kind of mismatches in LVS.
how the schematic netlist is getting updated?
As we don't do any kind of modification to the original schematic netlist,how that is getting updated?Or what exactly happening over there?
Please answer me...

Thanks and Regards
Manoj