[SOLVED] LVS mismatch for ncap family cell in GF130 nm

[Fávero Santos]

Hello, all!

I was helping a student in our lab with a LVS mismatch error while using ncap cell. I verified the log of the LVS (I am using PVS) and I observed that the pin map is being updated to a new one:

This happens when the option "DFII" is select in the "input" tab when using PVS GUI:

Here, I present a view of the graphical LVS debugger showing the mismatch due the pin map swap (red block: layout, pink block: schematic):

Interestingly, when I generate the CDL netlist in the schematic (via PDK->Netlisting->CDL->OK) and point the generated netlist file in the PVS GUI input tab, PVS run is clean:

LVS debugger view:

So, finally, my question is: what is going on and how to solve this issue in such a manner there will be no need to generate the netlist file and them upload it to the PVS GUI?

Many thanks!!!

Edit: added new images for future reference.

 

[Dominik Przyborowski]

Maybe you have to attach dedicated cdl for this device? Did you check process manual or at least pdk files for pvs?

 

[Fávero Santos]

Hi Dominik, based on your suggestion, I checked the subcircuit.cdl file that PVS calls when performing a LVS run. I observed that under dgncap, ncap pin definition, subckt was:

and I believe it should be defined as G SD B, right? I made a copy of the file and updated it to

and ran a new LVS run with the our standard LVS lab flow (by that I mean the auto-generation of cdls by DFII) but pointing the updated subcircuit.cdl file and LVS returned green!

Nonetheless, I could not locate in the server any documentation that could point that the subcircuit.cdl file should be updated nor I could find any mention of this issue on the README updates file. Perhaps the newer versions patch this issue?

 

[Dominik Przyborowski]

So, only Global knows the answer then.