lvs errors like bad net connnection

[monali P]

Hello s
I have designed a schematic and layout of dual input dual output comparator. I have completed Dry run successfully. But facing errors in lvs run.
Screenshots of errors and layout is attached with it..
Plz help me with a solution.
These are the screen shots

 

[kenambo]

I think you have done matching for the bottom two NMOS current mirrors with different Pins like vss and gnd.
May be it causes the problem.

Try the both MOSes with same vss connection and do matching. May be you get cleared.

 

[monali P]

actually I have given Vss supply to nmos current mirrors of first two differential stages.
And gnd is given to latch output stage.
Will this cause problem?

 

[kenambo]

Actually it is not a problem. But i think you matched those two transistors right?

If it is yes then bulk of these two devices must have same potential.

So it may cause the problem. So try to make it same gnd or vss then run and see the results.

thanks

 

[monali P]

Ok...I will try it....
Thanks....