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LVS error: schematic and layout mismatch. Port undetected.

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ahata14

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I am using the cadence version 6.1.3 with calibre tool. Furthermore I am using the open-source Design kit FreePDK provided in https://www.eda.ncsu.edu/wiki/NCSU_EDA_Wiki.
Herein is my problem: I can not obtain a clean LVS because I have some discrepancies. In the report says that one of the ports is undetected because of there is a short circuit between two nets in the layout.

WARNING: Short circuit - Different names on one net
Net Id:1
(1) name "gnd" at location (1.6,1.24) on layer 11 "metal1"
(2) name "out" at location (1.45,1.43) on layer 11 "metal1"
The name "gnd" was assigned to the net

I'll chech the layout circuit and those nets aren't connected to each other. Thus I dont' know how to correct this error. Maybe I didn't create the pin porperly.

If anyone can explain me how to properly connect the pins in this version of cadence it would be really kind.

Thanks in advance.
 

Re: LVS error: schematic and layout mismatch. Port undetecte

I think you can be rather sure that there exists a short circuit, either by pin label or due to a real short from "out" to "gnd", perhaps by "metal1" crossing a substrate tap.
Can you post (part of) the layout?
 

Re: LVS error: schematic and layout mismatch. Port undetecte

here goes the layout...By the way many thanks for your reply
 

Re: LVS error: schematic and layout mismatch. Port undetecte

Right, your NAND layout is clean. So perhaps an unintended/forgotten "out" label somewhere on the "gnd" node, may be even somewhere on the substrate (or pwell, if twin-well process)? Of course this isn't a real short circuit, just for the LVS. If you still mind, try and search for all "out" labels and check them.
 

Re: LVS error: schematic and layout mismatch. Port undetecte

I check this out but it seems that there is only one out label (which is the one needed). Maybe I am creating the pins incorrectly. May you tell me how to create a pin for cadence 6.1.3 ? Maybe I am not using the proper layer. I think that I tried all possible combinations though, but sometimes you are just missing the correct one. Btw, thanks for your help.
 

Re: LVS error: schematic and layout mismatch. Port undetecte

ahata14 said:
... Maybe I am creating the pins incorrectly. May you tell me how to create a pin for cadence 6.1.3 ? Maybe I am not using the proper layer. I think that I tried all possible combinations though, but sometimes you are just missing the correct one.
Sorry, I can't tell you more. May be you find more in this topic, and the links given there.
Good luck! erikl
 
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Re: LVS error: schematic and layout mismatch. Port undetecte

Looks as if there is no N+ implantation for NMOS.
 

Re: LVS error: schematic and layout mismatch. Port undetecte

pit1000 said:
Looks as if there is no N+ implantation for NMOS.
Sure, but the n-well implant is usually global for all standard cells (same height).
 

Re: LVS error: schematic and layout mismatch. Port undetecte

I meant ... (see picture)
 

Re: LVS error: schematic and layout mismatch. Port undetecte

I'm rather sure the ocher-coloured "w"-layer means p-substrate (or p-well).
 

Re: LVS error: schematic and layout mismatch. Port undetecte

erikl said:
I'm rather sure the ocher-coloured "w"-layer means p-substrate (or p-well).

Of course.
green-colored dot-filled layer - means ACTIVE (hole in mask oxide), seems like light blue-colored triangle-filled layer - means NIMPLANT layer (to form N+ areas). This last layer missed for NMOS. In result no N+ drain and source, only p-well through which "OUT" and "GND" shorted
 

Re: LVS error: schematic and layout mismatch. Port undetecte

pit1000 said:
green-colored dot-filled layer - means ACTIVE (hole in mask oxide), seems like light blue-colored triangle-filled layer - means NIMPLANT layer (to form N+ areas). This last layer missed for NMOS. In result no N+ drain and source, only p-well through which "OUT" and "GND" shorted
I think I see what you want to explain. For some processes, however, the NMOS implant layer is different (has lower implant dose) from the NIMPLANT layer (to form N+ areas in the n-well). For the lower concentration NMOS implant (in the p-substrate or p-well), the ACTIVE area ANDed with the p-substrate/p-well is used. Due to the slight under-diffusion (diffusion following the implant), the NMOS implant sufficiently surrounds the NMOS ACTIVE area. By this double utilization of the ACTIVE area layer, no further NMOS implant layer is necessary.
 

Re: LVS error: schematic and layout mismatch. Port undetecte

erikl said:
I think I see what you want to explain. For some processes, however, the NMOS implant layer is different (has lower implant dose) from the NIMPLANT layer (to form N+ areas in the n-well). For the lower concentration NMOS implant (in the p-substrate or p-well), the ACTIVE area ANDed with the p-substrate/p-well is used. Due to the slight under-diffusion (diffusion following the implant), the NMOS implant sufficiently surrounds the NMOS ACTIVE area. By this double utilization of the ACTIVE area layer, no further NMOS implant layer is necessary.

Maybe. I'm not familiar with FreePDK. I used the information from NCSU EDA Wiki.
 

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