ahata14
Newbie level 3
I am using the cadence version 6.1.3 with calibre tool. Furthermore I am using the open-source Design kit FreePDK provided in https://www.eda.ncsu.edu/wiki/NCSU_EDA_Wiki.
Herein is my problem: I can not obtain a clean LVS because I have some discrepancies. In the report says that one of the ports is undetected because of there is a short circuit between two nets in the layout.
WARNING: Short circuit - Different names on one net
Net Id:1
(1) name "gnd" at location (1.6,1.24) on layer 11 "metal1"
(2) name "out" at location (1.45,1.43) on layer 11 "metal1"
The name "gnd" was assigned to the net
I'll chech the layout circuit and those nets aren't connected to each other. Thus I dont' know how to correct this error. Maybe I didn't create the pin porperly.
If anyone can explain me how to properly connect the pins in this version of cadence it would be really kind.
Thanks in advance.
Herein is my problem: I can not obtain a clean LVS because I have some discrepancies. In the report says that one of the ports is undetected because of there is a short circuit between two nets in the layout.
WARNING: Short circuit - Different names on one net
Net Id:1
(1) name "gnd" at location (1.6,1.24) on layer 11 "metal1"
(2) name "out" at location (1.45,1.43) on layer 11 "metal1"
The name "gnd" was assigned to the net
I'll chech the layout circuit and those nets aren't connected to each other. Thus I dont' know how to correct this error. Maybe I didn't create the pin porperly.
If anyone can explain me how to properly connect the pins in this version of cadence it would be really kind.
Thanks in advance.