LVS Error in Cadence

[saikatchatrg]

Hi,

I am using cadence Virtuoso. After cleaning the DRC related issues I started LVS with the Layout. But I am getting the following errors.

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Layer SEED_inddif_hq_6U1x_2U2x_2T8x_LB DELETED -- LVHEAP = 25/415/618

Layer IND_DIF_HQ_nT_MP_M6 DELETED -- LVHEAP = 25/415/618

Layer IND_HQ_PORTS_LB DELETED -- LVHEAP = 25/415/618

Layer IND_HQ_RADIUS_nT DELETED -- LVHEAP = 25/415/618

Layer IND_HQ_CROSS DELETED -- LVHEAP = 25/415/618

Layer SEED_inddif_lohq_6U1x_2U2x_2T8x_LB DELETED -- LVHEAP = 25/415/618

Layer IND_DIF_LOHQ_1T_MP_M6 DELETED -- LVHEAP = 25/415/618

Layer IND_LOHQ_PORTS_LB DELETED -- LVHEAP = 25/415/618

Layer IND_M1SZ DELETED -- LVHEAP = 25/415/618

Layer IND_LOHQ_RADIUS_1T DELETED -- LVHEAP = 25/415/618


HIERARCHICAL SPICE NETLISTER
----------------------------
HIERARCHICAL SPICE NETLISTER completed. CPU TIME = 0 REAL TIME = 0 LVHEAP = 25/415/618 MALLOC = 225/225/386 ELAPSED TIME = 2

WRITING PHDB to directory svdb
PHDB WRITE completed. CPU TIME = 0 REAL TIME = 0 LVHEAP = 23/415/618 MALLOC = 226/226/386 ELAPSED TIME = 2

Layer ptapvia DELETED -- LVHEAP = 23/415/618

Layer ptap DELETED -- LVHEAP = 23/415/618

Layer psub DELETED -- LVHEAP = 23/415/618

Layer esdscr_nw DELETED -- LVHEAP = 23/415/618

Layer ntap DELETED -- LVHEAP = 23/415/618

Layer ntapvia DELETED -- LVHEAP = 23/415/618

Layer ncap_sd DELETED -- LVHEAP = 23/415/618

Layer NWtap DELETED -- LVHEAP = 23/415/618

Layer ttap DELETED -- LVHEAP = 23/415/618

Layer ttapvia DELETED -- LVHEAP = 23/415/618

Layer pcap_sd DELETED -- LVHEAP = 23/415/618

Layer TW DELETED -- LVHEAP = 23/415/618

Layer nband DELETED -- LVHEAP = 23/415/618

Layer NWT3 DELETED -- LVHEAP = 23/415/618

--- CALIBRE::HIERARCHICAL CIRCUIT EXTRACTOR COMPLETED - Thu Jan 29 12:16:48 2015
--- TOTAL CPU TIME = 1 REAL TIME = 1 LVHEAP = 23/415/618 MALLOC = 226/226/386 ELAPSED TIME = 2
--- PROCESSOR COUNT = 1

--- SPICE NETLIST FILE = /home/sachatterjee/lvsRunDir/inverter_hvt.sp
--- CIRCUIT EXTRACTION REPORT FILE = inverter_hvt.lvs.report.ext
--- PERSISTENT HIERARCHICAL DATABASE(PHDB) = svdb/inverter_hvt.phdb
--- QUERY DATABASE = svdb TOP CELL = inverter_hvt





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--- CALIBRE::LVS-H - Thu Jan 29 12:16:48 2015

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----- CALIBRE::LVS/xRC - INITIALIZATION MODULE -----
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Performing global initialization ...

Initializing LVS ...

--- CALIBRE::LVS/xRC INITIALIZATION MODULE COMPLETED. CPU TIME = 0 REAL TIME = 0 LVHEAP = 82/477/618 MALLOC = 227/227/386 ELAPSED TIME = 3

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----- CALIBRE::LVS/xRC - EXECUTIVE MODULE -----
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

LVS started ...

// Applying licensing policy...

// Licensed Products
// -----------------
// Base products running on 1 core:
// - LVS (Hierarchical)

READING layout ...
Layout READ. CPU TIME = 0 REAL TIME = 0 LVHEAP = 83/477/618 MALLOC = 227/227/386

READING source ...
Source READ. CPU TIME = 0 REAL TIME = 0 LVHEAP = 83/477/618 MALLOC = 227/227/386

Identifying CORRESPONDING cells ...
ERROR: Nothing in layout.

Writing REPORT ...
REPORT written. CPU TIME = 0 REAL TIME = 0

Cumulative READING INPUTS Time: CPU = 0, REAL = 0
Cumulative IDENTIFYING CORRESPONDING CELLS Time: CPU = 0, REAL = 0
Cumulative CHECKING PORTS Time: CPU = 0, REAL = 0
Cumulative REALLOCATING PINS Time: CPU = 0, REAL = 0
Cumulative WRITING XDB HIERARCHY Time: CPU = 0, REAL = 0
Cumulative ADDING GLOBALS Time: CPU = 0, REAL = 0
Cumulative RESOLVING DEEP SHORTS Time: CPU = 0, REAL = 0
Cumulative RESOLVING HIGH SHORTS Time: CPU = 0, REAL = 0
Cumulative DELETING TRIVIAL PINS Time: CPU = 0, REAL = 0
Cumulative FLATTENING Time: CPU = 0, REAL = 0
Cumulative TRANSFORMS Time: CPU = 0, REAL = 0
Cumulative REDUCTION Time: CPU = 0, REAL = 0
Cumulative GATES Time: CPU = 0, REAL = 0
Cumulative UNUSED Time: CPU = 0, REAL = 0
Cumulative COMPACTION Time: CPU = 0, REAL = 0
Cumulative COMPARISON Time: CPU = 0, REAL = 0
Cumulative MERGE PRIMITIVE TEMPLATES Time: CPU = 0, REAL = 0
Cumulative MERGE SUBGRAPH TEMPLATES Time: CPU = 0, REAL = 0
Cumulative NBD AND AMBIGUITY Time: CPU = 0, REAL = 0
Cumulative NBD Time: CPU = 0, REAL = 0
Cumulative INITIAL NBD IDS Time: CPU = 0, REAL = 0
Cumulative NEW NBD CONVERT Time: CPU = 0, REAL = 0
Cumulative NEW NBD BACK CONVERT Time: CPU = 0, REAL = 0
Cumulative NEW NBD ALG RUN Time: CPU = 0, REAL = 0
Cumulative NEW NBD IDS Time: CPU = 0, REAL = 0
Cumulative MATCH NBD NODES Time: CPU = 0, REAL = 0
Cumulative TPL Time: CPU = 0, REAL = 0
Cumulative BIN Time: CPU = 0, REAL = 0
Cumulative PRP Time: CPU = 0, REAL = 0
Cumulative AMBIGUITY Time: CPU = 0, REAL = 0
Cumulative AMBIGUITY BY PROPERTIES Time: CPU = 0, REAL = 0
Cumulative AMBIGUITY BY SUBTYPES Time: CPU = 0, REAL = 0
Cumulative AMBIGUITY HIERARCHICAL Time: CPU = 0, REAL = 0
Cumulative AMBIGUITY ARBITRARY Time: CPU = 0, REAL = 0
Cumulative REWIRE Time: CPU = 0, REAL = 0
Cumulative REPAIR Time: CPU = 0, REAL = 0
Cumulative REPORT Time: CPU = 0, REAL = 0


LVS completed. NOT COMPARED. See report file: inverter_hvt.lvs.report

LVS completed. CPU TIME = 0 REAL TIME = 0 LVHEAP = 83/477/618 MALLOC = 228/228/386 ELAPSED TIME = 3

ERROR: Corresponding cells could not be identified.


ERROR: Nothing in layout.


*** Calibre finished with Exit Code: 4 ***


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Please help me to get rid of the problem.

Regards
Saikat Chatterjee

 

[artmalik]

check the cell_name and top level name in the gds and cdl should match. from the error it appears that GDS doesn't have the cell at all.... you can do
strings <gds.filename>
it will give you the strings in the gds file....that should have the cdl top level subckt name.