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LVS error - help needed pins shortened

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lokesh garg

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LVS error

i m having a problem while doing LVS check. i made a layout of op-amp in UMC 180nm technology library, in whivh there are two separate pins gnd and vout in my schematic but in layout it is showing both of them connected, thats why it is giving error in LVS check. plz tell me what is the reason behind it...... thanks
 

bellona

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LVS error

looks like your gnd and vout are shorted.
 

lokesh garg

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Re: LVS error

yes. but in schematic these are not connected and i transferred schematic in layout using layout XL
 

bellona

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Re: LVS error

Once you have flatten any PCELL or things like that in XL, the connectivity information becomes weird in XL. That might led to layout mistakes later on. You can try short isolation in calibre
 

nelson_analog

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Re: LVS error

lokesh garg said:
yes. but in schematic these are not connected and i transferred schematic in layout using layout XL
In the schematic they are not connected, but in the layout they could be connect together accidently. So check you layout carefully.
 

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