Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

LVS error: block level C LVS matched but not on sub-block (d)

Status
Not open for further replies.

fixrouter4400

Full Member level 4
Joined
Feb 6, 2007
Messages
193
Helped
29
Reputation
58
Reaction score
6
Trophy points
1,298
Activity points
2,371
Hi all - maybe some of you did encounter this kind of weird errors in LVS.

Scenario:I have blocks A,B & C. and all of these blocks used the same sub block (d)
Sub block (d) I run the LVS in sub block level and LVS matched.
Now I run LVS for all the blocks A,B & C. then blocks A & B gave me lvs matched...but block C result said " LVS matched on C level but there's an LVS error on sub block (d) level..which is the same sub blocks I used on all levels.

it's wierd because it said that on block level C LVS matched but on sub block (d) isn't...with my understanding that if you have and LVS on sub block level your upper level block should give you an LVS error...which in my case doesn't give me unmatched errors.

Hope someone can help.
 

Re: LVS WIERD ERROR!

you might have error connections in the top hierarchy.
kindly post what exactly the error log file is.
thnks
 

LVS WIERD ERROR!

Thanks for the quick reply - but the thing is I have an LVS matched on top hierarchy level of block C and the wierd thing when I view the result it said the sub block (d) has problem on it...when in fact I did the LVS on sub block level (d) and LVS is OK and also I used the same sub block (d) for the blocks A & B and gave me an LVS matched.
 

Re: LVS WIERD ERROR!

this happens sometimes when u have errors in the top.
check if it really points to the lower hierarchy.
and what verification tool do you use?
 

Re: LVS WIERD ERROR!

:D
Is a fake error. Hercules from Synopsys give a lot of this. You will need to check all the error from the top of the cell C.
What LVS tool you use ?
 

LVS WIERD ERROR!

No it's not a real error in my layout. It's totally a bug in Assura verification tools....in some point the extraction tool cannot extract a series of 10 resistor...that's why it gives me this error...
 

Re: LVS WIERD ERROR!

Hi,
What kind of errors u have ??

A+
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top