Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

lvision model generation for clock gating cells in LV flow

Status
Not open for further replies.

pankaj_sawant

Newbie level 1
Newbie level 1
Joined
Jul 28, 2012
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,285
etlibgenerator tool provided by tessent LV does not support LV scan model generation of clock gating cells.

How to handle clock gating cells in LV flow?

How to provide definition of clock gating cells in ETChecker step of LV flow?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top