LVDS (and other high speed impedance matched signals) on an inner plane

[Smillsey]

Hi everybody

I have been designing a PCB which is essentially a measurement board which will interface to a seperate “processor” board driven by an FPGA.

There are several ADCs and a DAC needing LVDS routing.

I am primarily an analog designer working at less than 100MHz… But I need to route these LVDS lines to the board connector, the digital designers will handle the “FPGA PCB” after the board connector.

What I know;

1. I need impedance controlled traces at 100Ohm diff
2. Length matching
3. Reference plane adjacent to signal layer for return current (unbroken)

I am new to LVDS, so bear with me.

My Stackup will be as follows;


Low Freq. Signals
Power
Gnd
High Freq. Signals
High Freq. Signals
Gnd.
Power
Low Freq. Signals/Test Pads

My question is, if I need to get the signals from the top layer to the internal high speed signal layer, do I need to consider anything? Or can I just use vias directly next to all pins and worry no more?

thanks !

 

[KlausST]

Hi,

Some important basic parameters are missing:
* LVDS trace length total
* LVDS signal frequency

Then when the trace length < 0.1 × signal wavelength ... you don't need to take much care. Maybe raw impedance, maybe just series resistors...

Vias will cause impedance mismatch, but the "mismatch lentgh" is short, thus the signal distortion is low.

Klaus

 

[FvM]

In a design with LVDS signals (e.g. 400 - 800 Mbps speed), we have matched impedance differential pair rules both for outer and inner layers. Vias act as capacitive stubs, but they typically don't cause problems at sub-Gbps speed. At higher frequencies (e.g. SATA, USB3, PCIe), via backdrilling may be used to reduce parasitic capacitive load.

I see a possible problem in your stackup with the two adjacent signal layers. The scheme causes crosstalk and impedance variations depending on the interaction of differential pairs on both layers. It can work if you strictly avoid vertically parallel traces and restrict the number of crossings.

 

[Smillsey]

The data rate is 575MHz and length is going to be around 120mm max.

So I will need to control the impedance.

What I am struggling with is how allow for return currents when the trace passes through a via to another plane…

Im struggling to find good literature discussing how best to pass high speed signals through vias…

--- Updated Aug 7, 2021 ---

In a design with LVDS signals (e.g. 400 - 800 Mbps speed), we have matched impedance differential pair rules both for outer and inner layers. Vias act as capacitive stubs, but they typically don't cause problems at sub-Gbps speed. At higher frequencies (e.g. SATA, USB3, PCIe), via backdrilling may be used to reduce parasitic capacitive load.

I see a possible problem in your stackup with the two adjacent signal layers. The scheme causes crosstalk and impedance variations depending on the interaction of differential pairs on both layers. It can work if you strictly avoid vertically parallel traces and restrict the number of crossings.

thank you, I was going to have the two high speed layers configured so one is handling vertical and one is handling horizontal traces.

My reference for this 8 layer stack up was:

http://www.hottconsultants.com/techtips/pcb-stack-up-4.html

When the signal comes out of the LVDS pin on the chip, straight into a via, where does the return current flow around that via?

That reference mentions using ground to ground vias when you change layers 4 and 5 with a high speed signal, I’m just wondering what the situation is when you change from layer 1 to layer 4 with the via next to the signal pad at the chip.

 

[FvM]

There are no return currents for differential signals. The return current discussion in the link applies to single ended signals. It's good to have sufficient ground vias anyway.

 

[Smillsey]

Haha!

of course, now that made me feel stupid!

Thanks so much, I might post up my layout near the chip if that’s ok?

There are no return currents for differential signals. The return current discussion in the link applies to single ended signals. It's good to have sufficient ground vias anyway.

 

[senilicus]

Note that, especially for "lower" data rates, the rise time of the signal can still cause "high speed" problems.

- https://www.ti.com/lit/an/slla014a/slla014a.pdf?ts=1628483031151
- https://resources.altium.com/p/some-lvds-pcb-layout-guidelines-for-ensuring-signal-integrity
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp_lvdsboard.pdf

 

[Smillsey]

Note that, especially for "lower" data rates, the rise time of the signal can still cause "high speed" problems.

- https://www.ti.com/lit/an/slla014a/slla014a.pdf?ts=1628483031151
- https://resources.altium.com/p/some-lvds-pcb-layout-guidelines-for-ensuring-signal-integrity
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp_lvdsboard.pdf

Hi senilicus

yes we will be using series resistance to limit the rise time.

--- Updated Aug 9, 2021 ---

Note that, especially for "lower" data rates, the rise time of the signal can still cause "high speed" problems.

- https://www.ti.com/lit/an/slla014a/slla014a.pdf?ts=1628483031151
- https://resources.altium.com/p/some-lvds-pcb-layout-guidelines-for-ensuring-signal-integrity
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp_lvdsboard.pdf

Also, thanks for the references

 

[marce]

There are no return currents for differential signals. The return current discussion in the link applies to single ended signals. It's good to have sufficient ground vias anyway.

LVDS signals on a PCB are referenced to the adjacent plane so there is a return path, look at Howard Johnson etc. Every signal has a retrun current path.

 

[FvM]

The return path exists for common mode (even) signal only, it's ideally zero with LVDS. The return path for one differential wire is the other wire of the pair and vice versa.

 

[FvM]

Thanks to Marce for mentioning this great book HIGH-SPEED DIGITAL DESIGN - A Handbook of Black Magic.

They talk specifically about return path of differential signals in paragraph DIFFERENTIAL SIGNALING THROUGH A CONNECTOR

Differential signaling attacks the problem of signal return current not by providing a low impedance path for it but by eliminating it.
The theory of differential signaling is simple. Instead of transmitting one signal, transmit two. Send the signal you want, plus a second signal equal to the negative of the first. The return current from the first signal is positive. The return current from the second signal is negative. Together, they cancel.

 

[Smillsey]

Thanks to Marce for mentioning this great book HIGH-SPEED DIGITAL DESIGN - A Handbook of Black Magic.

They talk specifically about return path of differential signals in paragraph DIFFERENTIAL SIGNALING THROUGH A CONNECTOR

I have this book, I will have a re-read as I don’t recollect this section

 

[marce]

This is quite an interesting take on routing diff pairs...

Differential Routing

Is it better to route differential traces over/under (broadside) or side-by-side (edge-coupled)? Newsletter v2-30 11/11/1998(by Howard Johnson)

www.sigcon.com