LUT in VHDL is getting too many resources

[adina.manole]

LUT in VHDL is getting to many ressources

Hi,

I'm making a project where I need to use 4 different LUT. My FPGA is a Microsemi and I'm coding in Libero.
They have two by two the same input for the LUT (LUT1 and LUT2 has the same input and LUT3 and LUT4 have a different same input). LUT1 and LUT2 have 2305 values while LUT3 and LUT4 have 2185 values. Now, LUT1 is using 586 Logic Elements while LUT2 is using 196 Logic Elements and LUT3 is using 99 LE while LUT4 is using 453 LE.

I don't understand why there is such a tremendous difference between two LUT who are supposed to spend the same number of ressources. The only difference between them is the values inside the LUTs:
LUT1 : is going from FFF to 0 to FFF
LUT2 : is going from x"199" to FFF
LUT3 : is going from 0 to FFF
LUT4 : is going from x"199" to FFF

Thanks for your help

 

[ads-ee]

Re: LUT in VHDL is getting to many ressources

Your post is rambling and incoherent. I can't even determine if there is a problem besides a lack of understanding of the FPGA design flow and interpreting the resulting output log and reports files.

A simplified design flow consists of the following steps

• write RTL
• simulate (Microsemi Modelsim)
• create constraints
• synthesize in Symplify Pro (Microsemi synthesis)
• Implement the design in Libero (translation, place and route)

There should be no reason to be looking at the contents of the LUTs generated by the tools, unless you suspect a bug in the tools that is implementing the logic incorrectly (extremely remote, but I've seen this happen a few times over the course of 30+ years).

Maybe you should post a snippet of what you are looking at and misinterpreting, because I suspect things like "LUT1 and LUT2 have 2305 values" are using the terms like LUT and values incorrectly. and the "LUT1 : is going from FFF to 0 to FFF" is based on something entirely different then what you think.

 

[FvM]

Re: LUT in VHDL is getting to many ressources

The resource utilization of a look-up table implemented in logic cells will strongly depend on the actual table data because it undergoes the standard process of logic minimization during synthesis. A look-up table with little resource usage can be implemented in block RAM, provided your FPGA family has it.

 

[ThisIsNotSam]

Re: LUT in VHDL is getting to many ressources

The resource utilization of a look-up table implemented in logic cells will strongly depend on the actual table data because it undergoes the standard process of logic minimization during synthesis. A look-up table with little resource usage can be implemented in block RAM, provided your FPGA family has it.

this. your look up tables are being synthesised. why can't you use BRAMs?

 

[adina.manole]

Re: LUT in VHDL is getting to many ressources

There should be no reason to be looking at the contents of the LUTs generated by the tools, unless you suspect a bug in the tools that is implementing the logic incorrectly

The LUT are made by me in VHDL as follows:

if (RESET_N = '0') then
            lut_output  <= (others => '0');
        elsif rising_edge(mclk) then   
                 lut_output <= lut_data(to_integer(unsigned(lut_input)));        
         end if;

With the lut_data declared:

type lut is array (0 to 2184) of std_logic_vector(11 downto 0);
   constant lut_data : lut := (x"000",
x"001",
x"003",
--etc..

I have four different files for four different output of the LUT. What I was trying to understand is why for four LUTs (once again, coded in VHDL) with similar input/dimensions there is such a big difference between the resources they use.
In Synplify every file has a similar RTL view