LUP.2g DRC in tsmc 65nm technology

[guruprasadds]

Hi,

I had to face this myself a few weeks ago, if I remember correctly the problem occurred for all FETs using a supply from I/O (2.5-3.3V nom) rather than core voltage (1.2V) and we had to put rings around all NFET groups and PFET groups and separate them quite a bit

since this message only shows up when you turn on chip-level checks, it took us days to modify what was basically ready for submission

don't forget to run all exotic DRC checks as well we had to run 4 or 5 separate decks to sign-off...

Hi Dgnani,
I'm facing this problem at top level, i would like to know how to add these gaurd rings.
My I/O is separated by Core logic at top level, but as for this violation, Core is within 60um from IP OD injector.
So i face this violation at core logic.
I would like to know how to add these rings.

Thanks in advance.

 

[Subhash]

I understand these LUP.2g errors are at core cells and not IO.
- Adding Ptype guardings surrounding the effected NMOS in core area
- otherway could be adding guardRings (Ptype-Ntype-Ptype) for IO (For IOs because those are the injectors). this will eventually clear your LUP errors at core. Its a lengthy process though.

 

[guruprasadds]

Hi Thank you Subhash.
Since the core logic where i was facing this violation was almost had only fillers cells we removed it completely (its small region though).
Now im facing other LUP violation.
LUP.4 and LUP.5.0:1.5V__1.8V and LUP.5.6.0:1.5V__1.8V.
These violations are coming inside TXCLKDRV_PCIEREF cell kept near Top boundary.
For me Top Level stuffs are new, so im not able to understand wht it is and why they are coming.

Can you help me if to find out the possibilities to resolve this?

Thanks in advance. I have sent a request in skype. Please check.