Newbie level 5
I had to face this myself a few weeks ago, if I remember correctly the problem occurred for all FETs using a supply from I/O (2.5-3.3V nom) rather than core voltage (1.2V) and we had to put rings around all NFET groups and PFET groups and separate them quite a bit
since this message only shows up when you turn on chip-level checks, it took us days to modify what was basically ready for submission
don't forget to run all exotic DRC checks as well we had to run 4 or 5 separate decks to sign-off...
I'm facing this problem at top level, i would like to know how to add these gaurd rings.
My I/O is separated by Core logic at top level, but as for this violation, Core is within 60um from IP OD injector.
So i face this violation at core logic.
I would like to know how to add these rings.
Thanks in advance.