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LTspice simulation of Full bridge with synchronous rectifiers not working

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The following (attached) LTspice simulation of LTC3723-1 Full bridge SMPS with synchronous rectifier driver does not work properly when the synchronous rectifiers are added.

The simulation, which shows it working fine without the synchronus rectifiers, and mal-functioning when the synchronous rectifiers are added, shows the problem.

The dead times for the synchronous rectifiers do not appear to be correctly programmed into the Ltspice device models, and there is thus large shoot-through currents through the synchronous rectification FETs.

Do you know why this is happening?


  • Full Bridge _Sync Rectifiers.txt
    26.2 KB · Views: 101

Your design doesn't follow any Linear application circuit.

You are apparently ignoring important LTC3723 details, e.g. the inverted polarity of SDRA/SDRB signals.

Thanks, I see now, the LTC3723-1 needs to be used with the LTC3901, which also needs pulse transformer drive to its sync pin...otherwise some kind of logic circuituitry if not a pulse transformer.

I believe what is needed is a NEXOR gate to drive the fets with from the SDRA and SDRB outputs of the LTC3723....we don't want a pulse transformer in there as we will use a digital isolator

This is related to the above but not the same (it concerns the same chips, and a synchronous full bridge SMPS)

Do you know why the synchronous rectification can only be gotten to work properly when the LTC3901’s CSX+ and CSX- pins are all grounded?

The LTspice simulations attached here (“…good” and “…..bad”) show it working and not working, respectively, the ringed components are the difference between good and bad versions.

LTC3901 datasheet:

LTC3723-1 datasheet:


  • Full Bridge _SR_bad.txt
    19 KB · Views: 49
  • Full Bridge _SR_good.txt
    17.7 KB · Views: 64

The attached sync rect Full Bridge SMPS using LTC3901/LTC3723-1 now works, and the problem was with the SYNC signal not being of the right shape due to inductance of coupling coils of pulse transformer being too low.
However, there are now overvoltage spikes on the secondary diodes when in very light load. This is due to the secondary side sync fets not switching off before the primary side fets start to come on.
I have set the turn off delay of the secondary side sync fets to the absolute minimum via the RSPRG resistor, however, the problem still persists.
Anybody else having this problem?

Schematic of afflicted circuit attached (plus ltspice simulation)

- - - Updated - - -

Ahh, making the snubber a little “heavier” has solved it. Suspect there are multiple problems with reverse recovery of the sync rect fet’s intrinsic diodes…May I ask is there any experience of this?


  • Full Bridge _SR_works_3.txt
    19.5 KB · Views: 60
  • Full Bridge _SR_works_3.pdf
    35.2 KB · Views: 77
  • Full Bridge _SR_works_4.txt
    19.5 KB · Views: 57

Every senior power electronics engineer has their own tricks for making synch rect work properly...
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Thankyou, ..and one supposes that in that statement you are referring to sync rects after transformer isolated SMPS's and not sync rect's in eg buck converters?

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