; ====================================================
; 12b A/D converter subs...
;ANCLK = P1.0
;ANDATA = P1.1
;AINCS = P1.2
;AIN1L DATA 30h
;AIN1H DATA 31h
;AIN2L DATA 32h
;AIN2H DATA 33h
Read_AnalogInputs:
Ch0_Read:
MOV A, #0D0h ; 1101..CH0..
SETB AINCS ; CS must be H..
MOV B, #0Fh ; Time delay..
DJNZ B, $
CLR AINCS ; CS goes L..
MOV R4, #04h ; Load counter..send command to A/D
Loop_Ch0_1: RLC A ; Rotate Dbit into Carry..
CLR ANCLK ; CLK goes L..
MOV ANDATA, C ; Output Din/out..
SETB ANCLK ; CLK goes H..
DJNZ R4, Loop_Ch0_1
SETB ANDATA ; D becomes an input..
CLR ANCLK ; CLK goes L..
MOV R4, #05h ; Read 1dummy+4bits from A/D
Loop_Ch0_2: MOV C, ANDATA ; Read data bit into Carry..
RLC A ; Rotate data in ACC..
SETB ANCLK ; CLK goes H..
CLR ANCLK ; CLK goes L..
DJNZ R4, Loop_Ch0_2
ANL A, #0Fh
MOV AIN1H, A
MOV R4, #08h ; read remaining 8 bits from A/D..
Loop_Ch0_3: MOV C, ANDATA
RLC A
SETB ANCLK
CLR ANCLK
DJNZ R4, Loop_Ch0_3
MOV AIN1L, A
SETB AINCS
Ch1_Read:
MOV A, #0F0h ; 1111..Ch1..
SETB AINCS ; CS must be H..
MOV B, #0Fh
DJNZ B, $
CLR AINCS ; CS goes L..
MOV R4, #04h ; Load counter..send command to A/D
Loop_Ch1_1: RLC A ; Rotate Dbit into Carry..
CLR ANCLK ; CLK goes L..
MOV ANDATA, C ; Output Din/out..
SETB ANCLK ; CLK goes H..
DJNZ R4, Loop_Ch1_1
SETB ANDATA ; D becomes an input..
CLR ANCLK ; CLK goes L..
MOV R4, #05h ; Read 1dummy+4bits from A/D
Loop_Ch1_2: MOV C, ANDATA ; Read data bit into Carry..
RLC A ; Rotate data in ACC..
SETB ANCLK ; CLK goes H..
CLR ANCLK ; CLK goes L..
DJNZ R4, Loop_Ch1_2
ANL A, #0Fh
MOV AIN2H, A
MOV R4, #08h ; read remaining 8 bits from A/D..
Loop_Ch1_3: MOV C, ANDATA
RLC A
SETB ANCLK
CLR ANCLK
DJNZ R4, Loop_Ch1_3
MOV AIN2L, A
SETB AINCS
RET
; ====================================================