Feb 17, 2002 #1 J jimjim2k Advanced Member level 3 Joined May 17, 2001 Messages 996 Helped 23 Reputation 46 Reaction score 13 Trophy points 1,298 Activity points 7,178 Hi A Logic Verification and Debugging System A Formal Equivalence Verifier for Digital Circuits A Fault Simulation-Based Approach to Design Error Diagnosis 1. h**p://cadlab.ece.ucsb.edu/group_home/Downloads/Aquila_ErrorTracer/Manual.htm * -> t tnx
Hi A Logic Verification and Debugging System A Formal Equivalence Verifier for Digital Circuits A Fault Simulation-Based Approach to Design Error Diagnosis 1. h**p://cadlab.ece.ucsb.edu/group_home/Downloads/Aquila_ErrorTracer/Manual.htm * -> t tnx