LRU Worst performace scenario

[uditkumar1983]

Hi Friends,


What operation sequence makes LRU (Cache replacement policy) as worst in
performance.

OR

Say in other words that for which sequence willl make LRU policy as worst ...

Please help me on this ...

Thanks & Regards,
Udit Kumar

 

[trekkytekky]

If the depth of the LRU is so small that every page access generates a fault OR in other words, if every page access is for a page not already in the schedulers primary memory, therefore a page fault is generated and the LRU must be written to secondary and the new page written to primary.

 

[uditkumar1983]

Hi,

What you mean by "schedulers primary memory" is it mean cache memory ?

Why we need to do this "LRU must be written to secondary"..

We maintain LRU information together with the cache memory, and if there is a miss then we need to access data from secondary memory and data which was in cache will be replaced by new data so only one data transaction is happening ...

Can you please elaborate this is deatils ..

Thank you very much for my help ..

 

[trekkytekky]

The scheduler maintains a small table in primary (fast or cache) memory - usually RAM. As each Page is loaded, the Table is updated with the Pages Physical Address in primary memory RAM and the scheduler maintains the order of the list (LRU).

When we try to load a new page that is not in the table, a page fault will be generated. IF ALL primary memory available to the table has been allocated (RAM) we must write the LRU current page to secondary (Virtual - usually hard disk) then load the required page from Secondary to Primary. This is two Virtual access's at the slower access speed, as wanted and unwanted pages are swapped in and out of primary memory

Modern OS's use a Dirty bit as well as a Stealth write to try to eliminate one of these writes AT THE TIME of a page fault, but it doesn't always work.

Most modern CPU's used in mainstream computers have Memory Management Units (MMU's) built into them to assist the OS's implementation of the scheduler. Intel has GDT 's and LDT's as a basic example.

 

[uditkumar1983]

hi ,

thanks for your help ...