[SOLVED] LPRF design on 4 layers

[yolco]

Developing a new design on a 4-layer stack with reduced dimensions, there are some doubts I expect you can help me with.

• The board includes RF part, MCU, voltage regulator & battery charger.
• Power comes from an USB connector, then space need to be shared out not only with components as well as with power and signal lines.
• To avoid routing high current traces into inner layer, and make split planes, the idea is to maintain the high current power lines (VBUS, VBAT) into TOP layer. Routing to inner layer the low current power traces (VDD) and the signal ones.

For such design, two options are being considered.

1. TOP: components + high current PWR lines + signals; L2: GND plane; L3: PWR plane (VDD only); BOTTOM: GND + signals.
   • The doubt here is the differential pairs (clk, I2C, USB). Will the performance be affected in case of routing this kind of signals from TOP layer to BOTTOM & viceversa to not cross them with PWR traces?
2. TOP: components + high current PWR lines + signals; L2: GND plane; L3: GND plane + PWR (VDD only) + signals; BOTTOM: GND plane.
   • Doing at this manner, will the noise be increased? Will the differential pairs be affected (although they are shielded between GND traces/planes)?

Are one of previous questions suitable to accomplish the guidelines? Or there is another better option?

Kind Regards.

 

[ArticCynda]

I agree that USB is tricky, you'll definitely have to stick to differential pair design guidelines there. But I²C doesn't matter, if you're suffering from interference then reduce the pullups, and you can choose the bus frequency freely anywhere below 400 kHz. So if the data frequency is too close to other frequencies on the board and susceptible to interference, then just choose another frequency for the I²C bus.

The VUSB and VBAT traces may carry a high current but it's all DC so inductive interference won't pose a significant threat. As long as you give the traces a sufficient clearance to reduce capacitive interference, you won't have to worry about them. The maximum current is anyways limited by USB, which is 500 mA by default. That is hardly "high current".

 

[yolco]

Hi ArticCynda,

thanks for your quick response.

I2C is not a trouble then, it can be routed through bottom layer for avoiding to split L3 (PWR plane).
For USB data signals I look for differential pair design guidelines to ensure the design and data integrity.

About the current, I'm working with USB2.0, and limiting the maximum current to 1.5A. Even, if it is DC, this current needs relevant width, so I'm a bit worry to not forget anything for protecting the PCB from power dissation, heat...

 

[ArticCynda]

1.5A isn't all that much, what really matters is the voltage drop over a certain trace that is acceptable for your application. The narrower your trace, the higher its resistance and thus the move voltage will drop over it, acting as an unintentional resistor.

Take the trace 50 mil wide with 20 mil clearance, and you shouldn't have many trouble at all.

 

[yolco]

Hi,

I take into account your answers, to not damage the board.

Then, I'm going on with routing.

Regards!