LPDDR4 RAM speed reduced by half when boards are separated

[kakiitek]

Hi all,

Our system has two boards which are stacked on top of each other through a 60pin connector. The board at the Bottom consist of a simple 8 pin microcontroller which controls some peripherals. The Top board consist of the Ultrascale+, LPDDR4 (MT53D1024M32D4DT), Flash and power regulatory (buck) circuits.

When both Bottom and Top boards are stacked together, the speed of the LPDDR4 can reach 800MB/s. When these are NOT stacked together and interconnected through a cable (length 25cm, 60pins), the datarate reduced by half to 400MB/s.

This baffles us as the bottom board only channel the power rail enabling signals to the regulators on the Top board. Our measurement of the power sequencing on the Top board shows no significant differences with the power sequencing when stacked. Everything on the Top board runs, except for the reduced speed when separated.

Any ideas?

--- Updated Apr 23, 2023 ---

Just to add on.
The 60 pins connector consist of -

1. Power enabling pins (GPIO) x 20pins
2. USB and Display differential
3. Main supply (18V)
4. Grounds x20pins

When connected by the cable, we have separated the Main Supply of both boards just to confirm it has nothing to do with the ramping up time.

 

[FvM]

Fragmented ground on the top board?

 

[kaz1]

Hi all,

Our system has two boards which are stacked on top of each other through a 60pin connector. The board at the Bottom consist of a simple 8 pin microcontroller which controls some peripherals. The Top board consist of the Ultrascale+, LPDDR4 (MT53D1024M32D4DT), Flash and power regulatory (buck) circuits.

When both Bottom and Top boards are stacked together, the speed of the LPDDR4 can reach 800MB/s. When these are NOT stacked together and interconnected through a cable (length 25cm, 60pins), the datarate reduced by half to 400MB/s.

This baffles us as the bottom board only channel the power rail enabling signals to the regulators on the Top board. Our measurement of the power sequencing on the Top board shows no significant differences with the power sequencing when stacked. Everything on the Top board runs, except for the reduced speed when separated.

Any ideas?

--- Updated Apr 23, 2023 ---

Just to add on.
The 60 pins connector consist of -

1. Power enabling pins (GPIO) x 20pins
2. USB and Display differential
3. Main supply (18V)
4. Grounds x20pins

When connected by the cable, we have separated the Main Supply of both boards just to confirm it has nothing to do with the ramping up time.

One possibility to exclude is any floating pin which is driven when in full assembly but becomes floating if parts are separated. Try touch close to those pins and see any effect.

 

[kakiitek]

One possibility to exclude is any floating pin which is driven when in full assembly but becomes floating if parts are separated. Try touch close to those pins and see any effect.

Hi Kaz1,
The operation when it is stacked and when it is connected with cable are the same. As such, there is no change in the pins that are driven and those that aren't.
However, I think you have a point there which I would want to try. There are about 10pins on the 60pins connector that are unused and not grounded. These 10pins comes from the microcontroller from the bottom board and are channeled to the 60pin connector. However, on the top board, these pins are not connected to anything and appear as test points. I would try to terminate these to ground at the top board to see if it helps.
I wonder if such floating lines through the 25cm cable would be detrimental?
Many thanks.

--- Updated Apr 23, 2023 ---

Fragmented ground on the top board?

Hi FvM, would try to terminate those unterminated lines from the bottom board. On the top board, we have multiple inter layers of Ground plane. Let me now if you could think of more things that I could test on. Many thanks.

 

[FvM]

I have seen PCB with continuous ground plane that became fragmented due to unsuitable anti-pads in via pad stacks. In this situation, external ground connections might affect signal quality e.g. of RAM connections.

I was presuming that the design is completely under your control and there won't be unknown effects of unterminated FPGA signals and similar stuff.

 

[kakiitek]

Hi all,
Just to close this topic. There are two cables interconnecting both boards. One cable consist of 60 single ended lines and the second cable consist of 8 pairs of differential signals. It seems the data rate is back to it's designed maximum (800MB/s) after BOTH cables are connected.
It seems when only the single ended cable is connected, the LPDDR4 datarate reduces by half.
The differential cable carries non critical LVDS signal and as such was not connected earlier.

It will be interesting to know the reasons on why the datarate reduces by half -
1. The connection of the differential cable improves the grounding between the board? This is highly possible as there are a lot of ground pins on the differential cable. However, we did two test during earlier troubleshooting. One is where we power each board independently and with common ground. Second, we run a thick cable of similar length connecting the ground of both boards. If it was ground issue, shouldn't both method resolves the issue as well?
2. There are two LVDS lines coming from the Ultrascale+. When the differential cable is not connected, these lines are floating and not terminated. Would this have any effect on the datarate?

Thanks for all the suggestions!