Low Power (uW) Analog CMOS IC Design

[Puppet1]

Hello

I am looking for references on low power CMOS Analog IC and CMOS RFIC Design (for uW) applications...

the power is very low and thus the gm starts to go down significantly making frequency response hard...

any insights, papers, references ?

thanks

 

[borodenkov]

I think everyone is trying to reduce power now..
Which applications are you interested in?

 

[hrkhari]

Try reading the book on:

Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits, by Piet Wambacq and John Gerritel, publication by Kluwer Academic Publishers.

I found it to be quite beneficial. Hope this helps

Rgds

 

[yeewong_su]

Where can I find the e-book about it.

 

[EleApollo]

U may run the PrimePower of Synopsys corp to analyze the Power on your design, and improve on it.

 

[c_m_o_s]

Can anyone tell me where I can find an e-book of "Compact Low-Voltage And High-Speed CMOS, BiCMOS, And Bipolar Operational Amplifiers" by Klaas-Jan De Langen And Johan H. Huijsing.

thanks.

 

[Puppet1]

for telemetry style rf designs (this is the application)

that means getting data from say a weather station ...


anyway, quite simple.

that sansen book sounds good

does anyone have it ?

 

[cetc1525]

go to berkeley's website.

 

[selvaraja]

Hi
Do anyone have this book please upload in board ----- Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits, by Piet Wambacq and John Gerritel, publication by Kluwer Academic Publishers.

 

[Colbhaidh]

It may sound daft but some of the best recipes for low power are coming out of 65 and 90nm designs. Those processes leak so badly that designers have to be really innovative to reduce power. Taking their experience and translating it backwards gives really good tips for low power on say 0.18um. Techniques such as selectively turning off areas of the chip not immediately needed etc, high thrershold transistor etc

 

[Puppet1]

you would need a lot of power management then ? no wonder it's a hot area...

 

[mbright]

hi Colbhaidh

once again, i'm confused.

As power consumption in analog IC is mainly due to DC biasing (and the biasing current is always there), why bother the leakage?
It’s true, that makes the transistor a bad switch, and will cause signal leakage, CFT etc. But those r performance issue, not power.


As for digital, most of time, there should be no DC current at all.
i heard the leakage will consume 50% of the totally power in 90nm or less, so those tech. may badly needed by digital designer.

 

[riz_aj]

leakage current for 90nm process is 100nA per transistor. for big chip like prescott that has 152million transistor, that counts for 15.2mA just for leakage current.