[SOLVED] Low power optimization problem in competitive vendor economics ?

BeckettColt said:

Suppose the power saving of design is D, which is supposedly lower than current benchmark systems. Suppose such design provides a good compromise of speed. memory and power

Suppose i added nop instruction(no instruction instruction) into the microprocessor. Since nop now provides an advantage over other systems. by survival of fittest logic, if i choose to replicate nop type power reduction scheme. not only would an copy be slow, it would also consume more power from replication of N number of nops.

Several schemes use survival of fittest logic( just psychology to choose winner), for example: Michael hsiao, sequential atpg using hadamard, Niermannn's hitec..

Click to expand...

BeckettColt said:

Suppose the power saving of design is D, which is supposedly lower than current benchmark systems. Suppose such design provides a good compromise of speed. memory and power
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Suppose i added nop instruction(no instruction instruction) into the microprocessor. Since nop now provides an advantage over other systems. by survival of fittest logic, if i choose to replicate nop type power reduction scheme. not only would an copy be slow, it would also consume more power from replication of N number of nops.

Several schemes use survival of fittest logic( just psychology to choose winner), for example: Michael hsiao, sequential atpg using hadamard, Niermannn's hitec..

Click to expand...