low power/high speed design?

[triquent]

what is the place and route methodology suggested from your point of view in implementing low power/high speed design?

 

[bravobravo]

from design methodology : such as
1. Power management Unit
2. use tools to gate your clock ...first in frontend the ..check and fix in beckend .
3. use different Voltage cell library in VDSM design
4. use variant voltage in your design and manage it
..
..

Hope this help.

 

[richardwan]

low power : gated control
high speed: pipelined control

 

[eejli]

is it anturally a tradeoff?

low power plus low voltage means low current while circuits need big current to run faster.

 

[SkyHigh]

not really for to have "big" current for circuits to run faster.

to make circuits run faster, you need:
1. processing-efficient architecture and circuits, usually simple circuit, parallel and pipelined architectures
2. increased operating clock or frequency

there is however a very scientific way of saying, "you need more power for a system to run faster" and this is proven and true.

Since speed is a function of power, and power is a function of current and voltage. Either you increase I or V or both to increase speed.

 

[soccer]

it is not a simple issue for the high speed circuit design, i suggest you to look up some methology books or papers in this point for reference.

 

[triquent]

the question about low power/high speed design is only from P&R point of view.

 

[dynamicdude]

Sometimes you can also tweak your clock routing to use the "useful skew" concept to raise the frequency, however care should be taken to eliminate the side effects.

Also the combination of MTCMOS/Voltage islands can give excellent results I supose.

 

[Thomson]

I think that the methods in addition to those mentiond above, the major consideration is that pay more attention to the high-speed portion, which will use high-frequence and more power. For the low speed portion, the lower frequency shall be used just as implemented in the PC system, where the CPU and cache use the higher frequncy mulitplied by a lower frequence. Only the CPU is active, then the clock is on; and if not completely active, then the frequency shall be lowered; and even the power can be off.

From this point of view, you have some systematic idea of your design and cooperation with the software implmentation.


In addition, some low-power skills such as slicing the DRAM addressing, using as small FFs as possible to reduce the load of the clock pins since the clock toggle power accounters for much of the percentage of the whole power dispation.


In short, you shall consider this problem from top-to-down .