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low power design with UPF & DC

YakDamBam

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I have a question
I'm designing a 32bit RCA applying low power design(retention cell, isolation cell, power swtich)

So I want to measure power of my design, does it decrease even if I measure it after only synthesis(DC) before implementation(ICC)?
 

ThisIsNotSam

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it is not always trivial to give power intent information to logic synthesis. it is easier to do block-level synthesis of the RCA and get power reports later from physical synthesis
 

YakDamBam

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it is not always trivial to give power intent information to logic synthesis. it is easier to do block-level synthesis of the RCA and get power reports later from physical synthesis
So you mean measuring power after P&R is more accurate than after synthesis?
 

ThisIsNotSam

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In logic synthesis, it is hard to describe the power intent. You usually deal with blocks during logic synthesis, but you are interested in measuring the power of all blocks at the same time. They only really exist at the same time in the SoC, meaning during physical synthesis.

It is true that you can write a UPF file and pass that to logic synthesis. It is not impossible. But that file is helpful for setting corners and maybe some retention/level shifter settings. It does not help you to determine the power consumption of the SoC in its many possible functional configurations.
 

YakDamBam

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In logic synthesis, it is hard to describe the power intent. You usually deal with blocks during logic synthesis, but you are interested in measuring the power of all blocks at the same time. They only really exist at the same time in the SoC, meaning during physical synthesis.

It is true that you can write a UPF file and pass that to logic synthesis. It is not impossible. But that file is helpful for setting corners and maybe some retention/level shifter settings. It does not help you to determine the power consumption of the SoC in its many possible functional configurations.
Thank you for your answer

As far as I understanding writing UPF and synthesizing with UPF is helpful but it doesn't mean useful for measuring power comsuption?
Is it right?

And I have one more quesiton
As far as I know, when synthesizing I have to add input and output register for accurate timing measurement
Is it applied same for when power measurement?
 
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luoyanghero

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I have a question
I'm designing a 32bit RCA applying low power design(retention cell, isolation cell, power swtich)

So I want to measure power of my design, does it decrease even if I measure it after only synthesis(DC) before implementation(ICC)?
In logic synthesis, it is hard to describe the power intent. You usually deal with blocks during logic synthesis, but you are interested in measuring the power of all blocks at the same time. They only really exist at the same time in the SoC, meaning during physical synthesis.

It is true that you can write a UPF file and pass that to logic synthesis. It is not impossible. But that file is helpful for setting corners and maybe some retention/level shifter settings. It does not help you to determine the power consumption of the SoC in its many possible functional configurations.
For RTL syn level, we want to know power distribution and power optimization space in RTL design. Does not need to the accurate power value. Can use a tool(like spyglass or VC_spyglass, not UPF) to get the power distribution?
 

YakDamBam

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For RTL syn level, we want to know power distribution and power optimization space in RTL design. Does not need to the accurate power value. Can use a tool(like spyglass or VC_spyglass, not UPF) to get the power distribution?
Do you mean what tools I use?
I use VCS, DC and Primetime(PrimePower).
 

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