low power design techniques in vlsi

[santoshvaddisetty]

Hi All,

can anyone give a short note related to low power vlsi design techniques pertaining to front end design.Give me a short note on "CLOCK GATING" as well.

 

[xiaowoliu]

at RTL design, i think the low power techniques are very few and not obvious , if at system level or algorithm level is better than it, i think

 

[jeevan.life]

Clock gating is a technique used to turn of some blocks which are inactive. You will need to have clock gating cells which can cut off clocks from reaching these areas hence reducing the switching power for that domain. I am not much informed about the front end power saving methods.

 

[mail4idle2]

While designing Architecture you can aim for low power. Multi Vdd is another option which come again at Architecture level.

 

[yadavvlsi]

Here are some low power techniques.
1. Architectural Level: Pipelining and asynchronous.
2. Design Level: Multi VT, clock gating, power gating, multi VDD and DVFS.
3. Process Technology: Silicon on Insulator, multi VT, Body Biasing, FinFET.

Search in google to know details of each technique .

 

[HPC]

To achieve low power as far as front end is considered, do the following
1. Use clock gating for blocks e.g. Register interface which is not used often.
2. Minimize transitions on buses. If possible, use grey encoding or do not change address on address kine if not required.
3. Use resources sharing.
4. In your state machines, of no of states are not large, go for one hot encoding.
5. Use register retiming.
6. Use enable for your counters. Do not allow them to run when not used.

 

[CHGK.24]

Kindly can share the documents related to system level or algorithm level

Thanks in advance

 

[mutant_corpse]

Some low power techniques are Clock Gating and Power Gating.
Refer to these posts:
1) https://vlsi-soc.blogspot.in/2012/08/clock-gating-integrated-cell.html
2) https://vlsi-soc.blogspot.in/2012/07/clock-gating.html
3) https://vlsi-soc.blogspot.in/2012/08/power-gating.html
4) https://vlsi-soc.blogspot.in/2013/03/state-retention-power-gating.html