[SOLVED] Low Power Design Flow Questions

[csjiang]

Dear all:
I am studying the Synopsys "low power design flow". There are some questions list below need your help.

1. I create UPF file for Design Compiler to describe power domains of my design. One power domain (PD1) can be normal supplied or turned off, one domain (PD2) is always on but can be reduced voltage level when PD1 is off. After I load UPF file, will the design compiler capture the knowledge that PD2 has two power levels and perform synthesis on both voltage levels cases to optimize my design? Or I need to create scenarios to perform multi-voltage optimization flow?

2. If I need to create scenarios to perform multi-voltage optimization, how should I describe the case that PD1 is turned off and PD2 is at lower power voltage level? "set_voltage 0" on the supply net of PD1? Or I need to set false path on the paths of crossing PD1 and PD2?

Thank you for your help.

 

[artmalik]

This requires a combination of definition in the multi-mode and multi-corner mode. There has to be multiple modes
mode 1 : PD1 vdd1=1.0v , PD2 vdd2=0.5v
mode 2 : PD1 vdd1=0v , PD2 vdd2 = 1.0v
etc.....
in each of the cases the timing will be verified if it is met. also the interconnections are checked whether the two blocks are properly isolated and required outputs are clamped as needed. UPF syntax may not cover everything, it will be combination of CPF and UPF where CPF models check the voltage range/reset states etc. There are Conformal tools which check the basic operation connectivity in the modes. The constraints for the connectivity and proper operation is part of the conformal verification.
multi-voltage : Connectivity constraints followed timing is done by a set of tools(many are done through scripts)

 

[csjiang]

Dear artmalik:

1. Do you mean I need to create scenarios and run on multi-mode multi-corner for synthesis (using design compiler)?
2. My 2nd question is that I doubt whether timing checking tool can recognize timing paths from/to PD1 are false paths when PD1 voltage is set to 0v. Or I still need to set all paths from/to PD1 are false?
3. By the way, you mentioned CPF. As I know, CPF is Candence's low power script. If I use Synopsys' tool (DC, PT, formality), shall I still use CPF?

Thank you for your reply.

 

[artmalik]

Yes, there will be multi-mode multi-corner analysis although synthesis can done with one corner which you think is critical but the final sign off has to be done with all the corners and modes. If the VDD1 is 0 for one block the tool will not have a .lib with 0v so it will not do any timing.
CPF is may not fully supported with Synopsys but it is a new low power standard.
https://standards.ieee.org/findstds/standard/1801-2013.html
So many of the commands may not be supported as this is a new standard. But I think you can always write tcl scripts to support the design constraints in Synopsys tools ...if you had Conformal then the tool would have checked many things automatically.