Nov 23, 2006 #1 B blowfish Member level 4 Joined Jul 20, 2006 Messages 77 Helped 3 Reputation 6 Reaction score 2 Trophy points 1,288 Location INDIA Activity points 1,829 verilog commutator HOW TO IMPLEMENT THE FSM(ROM + COUNTER) IN THE PAPER SHOWN " Low Power Commutator for Pipelined FFT Processors". I HAVE UPLOADED THE PAPER ALSO . ANY SUGGESTION OR IDEAS REGARDING IMPLEMENTING THIS MODULE . THANKS IN ADVANCE
verilog commutator HOW TO IMPLEMENT THE FSM(ROM + COUNTER) IN THE PAPER SHOWN " Low Power Commutator for Pipelined FFT Processors". I HAVE UPLOADED THE PAPER ALSO . ANY SUGGESTION OR IDEAS REGARDING IMPLEMENTING THIS MODULE . THANKS IN ADVANCE
Dec 27, 2006 #2 B blowfish Member level 4 Joined Jul 20, 2006 Messages 77 Helped 3 Reputation 6 Reaction score 2 Trophy points 1,288 Location INDIA Activity points 1,829 implementation in verilog Hi, Can anyone send me the key concepts involed in low power design of fft processor. It contains 1. low power commutator 2.low power multiplier 3.low power butterfly if anyone has worked on it , send me the codes also verilog/vhdl
implementation in verilog Hi, Can anyone send me the key concepts involed in low power design of fft processor. It contains 1. low power commutator 2.low power multiplier 3.low power butterfly if anyone has worked on it , send me the codes also verilog/vhdl