Low offset Comparator

[Chinnu17]

I wanted to design a low offset comparator(<1mv) and <20ns processing time and ICMR of 0.7 to 2.4v. Please help me the steps to follow in designing and what should be considered in main priority. Thank you.

 

[Easy peasy]

not going to get there with cmos are we ... ?

 

[frankrose]

Look for auto-zero offset cancellation of comparator. With some low gain high bandwidth preamplifier your requirements are feasible I think.

design hint: https://aicdesign.org/wp-content/uploads/2018/08/lecture33-140626.pdf

 

[dick_freebird]

You need to take advantage of external resources and a activity, first knowing what these are, offer and preclude.

Clocked comparators can embed auto-zero in the latched phase and get to <100uV easily. Continuous-time comparators make it tougher to hide and fold in any offset cancellation although you could (say) ping-pong two comparators, nulling one while the other is active and flipping on output transitions.

Expecting testability when embedded in a SoC at a 1mV limit spec, is probably misguided.

Point is, basic CMOS analog design is only the smallest part of the picture. You have to fit and make best use if your application environment.