Hello! Can anyone suggest a number of rules to observe when designing a low noise synchronous digital circuit at front-end level? E.g. gray counter usage. Back-end design tricks are also welcome (e.g. clock skew control).
Gray coding is good. Also use a spread-spectrum PLL to generate the clock if possible. Large, evenly-distributed clock skew helps too. Use lowest voltage possible, and slowest clock speed possible. PCB layout is important too (use a whole ground plane or more than 1 if possible.) Use a hefty power grid and plenty of ground pins. Use decoupling capacitors on the PCB and on the die itself if available. Then shield everything multiple times.