tia_design
Advanced Member level 4
low noise cmos op amp design
You guys,
I'm designing a low noise CMOS Op Amp, now I can reduce thermal noise (input referred) down to 1.5nV/rhHz, this is schematic simulation result. I don't know how much additional noise will be added after layout. Does anybody do the simular research so we can discuss it?
You guys,
I'm designing a low noise CMOS Op Amp, now I can reduce thermal noise (input referred) down to 1.5nV/rhHz, this is schematic simulation result. I don't know how much additional noise will be added after layout. Does anybody do the simular research so we can discuss it?