Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Low input offset voltage op-amp!

Status
Not open for further replies.

rficdesigner

Member level 2
Joined
Jun 17, 2008
Messages
52
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Korea
Activity points
1,592
Dear all,

My targeted op-amp designed in CMOS has input offset voltage ~ 100 uV.

I am looking for some techniques for minimizing the input offset voltage of the op-amp.

If you have any idea please share.

Thanks and have nice time!
 

rajanarender_suram

Full Member level 4
Joined
Jan 20, 2006
Messages
215
Helped
22
Reputation
44
Reaction score
9
Trophy points
1,298
Activity points
2,375
find the attached paper for reference, u will be able to acheive 100uV offset with this architechture
 

kwkam

Full Member level 5
Joined
Feb 25, 2002
Messages
276
Helped
30
Reputation
60
Reaction score
13
Trophy points
1,298
Location
Somewhere on earth
Activity points
1,879
the paper only talk about the systemic offset, at the level of 100uV. The random offset will kill you. The only way to attack this problem is using bipolar input stage or trimming.
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
7,281
Helped
2,126
Reputation
4,257
Reaction score
1,983
Trophy points
1,393
Location
USA
Activity points
58,397
The nominal offset being low, is nice - but figure you
will have device mismatch in the few to 10mV range
and you'll need some sort of active cancellation to
get a +/-100uV "stovepipe" distribution.

Nice paper though.
 

edge_tv

Member level 1
Joined
Apr 29, 2008
Messages
38
Helped
8
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
1,508
Hi look for the paper from C. C. Enz and G. C. Temes "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization". It is good summary. Or papers from delft U. they do also a lot of this stuff
 

rajanarender_suram

Full Member level 4
Joined
Jan 20, 2006
Messages
215
Helped
22
Reputation
44
Reaction score
9
Trophy points
1,298
Activity points
2,375
kwkam said:
the paper only talk about the systemic offset, at the level of 100uV. The random offset will kill you. The only way to attack this problem is using bipolar input stage or trimming.

as the area of input pair increases the random off-set also decreases, and this kind of circuit is implemented to get 50uV of off-set on silicon,, important thing in the design is the tail-current impedence of the input-pair is high and the input pair area has to be large even though they work in sub-threshold region
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top