Low frequency multi-phase clock generation

[rfdipper]

Please help generate a multi-phase clock in the order of KHz from a reference clock input?
:?: :?:
Simple RC delay will not work at some duty cycle while using the propagation delay of logic gates will not be practical since I need milliseconds delay while propagation delay is in the nanoseconds range .

Your reply will be greatly appreciated.

 

[dumbfrog]

some suggestions on pll or dll.
is pll or dll too big for your design?

 

[flatulent]

To amplify the previous post, have the PLL operate at a multiple of the input clock. Use a counter in the feedback to the phase detector. Decode the counter states to get your clock phases.

 

[super]

How about use Ring OSC ?
in each stage add cap for lower down frequency.

 

[rf_ray]

for delay at millisecond level, it's not likely you can realize it using a simple delay cell. Probablly some kind of finate state machine can do that I think.