Looping over a 3d Systemverilog array

[shaiko]

Hello,

I have a 3d array defined as :

logic [1:0] [2:0] [3:0] some_3d_array  ;

I want to write a "foreach" loop that iterates over all dimensions.
Is this the correct syntax ?

foreach (some_3d_array[i])
begin
    foreach (some_3d_array[i][j])
    begin
        foreach (some_3d_array[i][j][k])
        begin
        // do something
        end
    end
end

 

[dave_59]

No. This syntax is not legal event if some tools allow it. You'll wind up iterating over the first dimension 3 times.

If you only want to do something at the inner most loop, you can do

foreach (some_3d_array[i,j,k])
      begin
      //do something 
     end

But if you really need 3 separate loops, you can do

foreach (some_3d_array[i])
begin
    // do something over i
    foreach (some_3d_array[,j])
    begin
        // do sometthing over j
        foreach (some_3d_array[,,k])
        begin
        // do something over k
        end
    end
end

 

[shaiko]

Thanks dave_59.
What if my loop was defined as :

logic [1:0] [2:0] some_3d_array [3:0] ; // one unpacked dimension

How would the code change ?

 

[dave_59]

The foreach loop would not need to change. See section 12.7.3 The foreach-loop in the IEEE 1800-2017 SystemVerilog LRM