There are two possible reasons why the current source circuit has instability that doesn't show in your loop gain simulation:
- different output current and thus different MOSFET gm between loop gain simulation and actual operation
- dynamic instability caused by OP and MOSFET large signal behavior
The loop gain "measurement" circuit looks overly complicated to me, I would refer to a simple Middlebrook's setup with a series stimulation voltage source.
Yes, we see that, just we are not sure that the small signal equvivalent explains the large signal oscillation now. We cannot sure this overcomplicated test explains the large signal behaviour.
To move the transistor from triode region to saturation increase the V7 source voltage to 10V for example, should be enough.
I can't check the loop gain of your circuit because I don't know which transistor model you are using. It's not shipped with Ltspice. See below a simulation with a 100V 8mOhm MOSFET.But as far as I can tell, the loop gain simulation is showing that the loop is very unstable.
I can't check the loop gain of your circuit because I don't know which transistor model you are using. It's not shipped with Ltspice. See below a simulation with a 100V 8mOhm MOSFET.
View attachment 149649
The loop gain is cut down by Ciss in combination with low impedance and showing no problems, large signal behavior may be critical, though. I'm posting the schematic primarily to show the loop gain measurement setup.
Before suggesting compensation circuits etc., I would like to understand the application requirements (speed, current range).
Unfortunately not, may be others have suggestions.do you have any reference for me to look at so that I will be able to perform this type of compensation myself with different output impedances and mosfets?
Unfortunately not, may be others have suggestions.
I concede that the rather low compensation network corner frequency of about 3 kHz is counter-intuitive at first sight for a 3 MHz OP. But it's actually required to bypass and "neutralize" the weird transfer function of the MOSFET with output load. There are other possible ways to "tranquilize" the circuit, e.g. a RC snubber in parallel to the output inductance.
If your application requires a higher current source bandwidth, an OP with higher bandwidth and lower output impedance would be required.
Just from curiousity, but how is the step-response with 1.25V drain voltage? Was it solved? If not, and the compensation method is finalized I would mention that you can connect paralel MOS devices to decrease the Vdsat. It will increase the output headroom, the gate capacitance, but with the correct compensation last shouldn't be a problem.
The limiting factors for stable current source bandwidth are OP output impedance, OP bandwidth and MOSFET Ciss.
I didn't yet hear a specification of maximal output current, you should select a suitable MOSFET with sufficient but not overly low Rdson. Also with Vds,max according to the maximal required output voltage. A 100 V MOSFET isn't a good choice.
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