I am happy not only my Cadence is doing things which are nonsense. I also experienced this, with a similar rail-2-rail class-AB OPAmp, very strange behaviour.
However I couldn't explain it yet in 100%, the present situation or conclusion is that it is not a problem, only appears in AC and STB analysis, and next to certain input variable conditions (stability parameters are still fine, transient oscillation doesn't appear) and probably it is only a modelling issue.
For example, if you run PVT corners probably the phase will start from 180° in some of them, or if you change the load, or change input common mode DC level, etc.
Other strange thing which you can experience is the DC gain can rapidly increase with certain resistor load values and with different input/output DC levels.
I figured out finally that this circuit's speciality, the floating current sources (or Monticelli class-AB biasing) cause these, and interesting that the BULK effect of the floating current source.
Try to connect the biasing diode's BULK to its SOURCE on the NMOS and PMOS side, and connect the BULKs on the floating devices to the SOURCE too, so quiescent current in the output stage won't change, but probably the phase will start from 180° as it should in every PVT corners, with any load and every DC level.
I am not sure about the exact reason and this solution, I didn't have enough resources to check every operating parameters, but I know it solved.
Please won't hesitate to write if you know anything about this.