lookout for data on chip/die space occupied by flash memory.

[hikaan]

Hi

Is there any formula between flash memory capacity Vs die space occupied?

Thanks

 

[erikl]

Sure: for every process size, technology and flash type (NAND, NOR, ...). Foundries know it.

 

[dick_freebird]

I have seen a lot of variation in layout, from just a little looking.

I don't think there is a good general formula, and believe cell
design will be somewhat ad hoc / "what works" driven - the
design will push density until reliability is (unacceptably)
compromised, and this involves processing (recipe and the
consistency of outcome, and use-model) as well as polygons.

You could probably come up with an empirical relation by
surveying bit counts, die sizes and making some assumptions
about overhead (but you will need the same overhead, so
maybe don't bother trying to trim the fat). In the end, though,
you'll probably be combining disparate nodes and foundry flows
and maybe you don't care at all about "legacy" (45nm is so
2013) densities?

Now, foundries doing ASIC business like to brag about cell
density, you'll see things like compiled RAM bit densities as a
sales figure-of-merit and I'd expect the same of any EE bank
IP. If you can drill down to the ASIC marketing collateral you
might find what you want, for the flows you care about, from
the foundry's actual implementation.