Availink1
Newbie level 4
Sr. Physical Design Engineer Opening - DC/Metro area
Company Introduction: Availink Inc. is a technology-driven fabless semiconductor company, focusing on the multimedia and digital TV industries. Availink is backed by premiere financial institutions, with offices in China and the United States and with targeted consumer markets around the world. By grouping a great team of professionals, building multiple product lines in fast growing markets, and attracting beachhead customers, Availink is positioned to grow into a significant player in the field. If you are hands-on, results-oriented, energetic and eager for an opportunity to learn and strive to achieve the best results, Availink will offer you a challenging and rewarding career.
Position Tasks, Duties and Responsibilities
The ASIC Physical Design Engineer will:
•Perform full synthesis (RTL synthesis, place & route) of standard cell IC.
•Perform library, IP, and IC design service evaluation and selection.
•Complete third party IP integration and ensure vendor guidelines are followed.
•Work with front-end engineers to resolve problems and achieve design closure.
•Adhere to established design methodology and contribute to its continuous improvement
•Use scripting languages, configuration management, batch processing, and other techniques to ensure design quality and minimize turnaround time
Responsibilities include:
•Front End synthesis
•IC physical design flow
•Floorplanning and power grid implementations
•Placement of standard cells
•Scan insertion / scan chain reordering
•Creation and placement of memory macros
•Analog IP integration
•Power mesh creation and analysis
•Clock tree synthesis
•Routing
•Parasitic extraction
•Timing verification
•Timing improvements for critical macro blocks
•Timing closure
•Noise analysis
•IR drop analysis and power estimation as required
•LVS/DRC
•Implementation of ECO changes
• Equivalence checking – RTL to gates, and gates to gates
Candidate Qualification Requirements
Candidate must:
•Hold BSEE (MS preferred).
•Have minimum of 5 years hands-on experience in IC back-end physical design and verification.
•Project or team management skills including scheduling, resource management, and progress reporting
•Have at least 2 years using Magma place and route tool.
•Have completed hierarchical IC projects in 90 nm and below.
•Have the ability to independently identify and resolve design, tool, and flow problems
•Be able to design and implement physical design strategies and methodologies for deep submicron designs.
•Be able to complete block and chip level LVS and DRC
•Exhibit good written and verbal English skills and ability to work with internal and external design teams.
Any of the following is beneficial:
•STA constraint design
•Conversational in Mandarin dialect
If you are interested, please email with your resume: careers_us@availink.com
Company Introduction: Availink Inc. is a technology-driven fabless semiconductor company, focusing on the multimedia and digital TV industries. Availink is backed by premiere financial institutions, with offices in China and the United States and with targeted consumer markets around the world. By grouping a great team of professionals, building multiple product lines in fast growing markets, and attracting beachhead customers, Availink is positioned to grow into a significant player in the field. If you are hands-on, results-oriented, energetic and eager for an opportunity to learn and strive to achieve the best results, Availink will offer you a challenging and rewarding career.
Position Tasks, Duties and Responsibilities
The ASIC Physical Design Engineer will:
•Perform full synthesis (RTL synthesis, place & route) of standard cell IC.
•Perform library, IP, and IC design service evaluation and selection.
•Complete third party IP integration and ensure vendor guidelines are followed.
•Work with front-end engineers to resolve problems and achieve design closure.
•Adhere to established design methodology and contribute to its continuous improvement
•Use scripting languages, configuration management, batch processing, and other techniques to ensure design quality and minimize turnaround time
Responsibilities include:
•Front End synthesis
•IC physical design flow
•Floorplanning and power grid implementations
•Placement of standard cells
•Scan insertion / scan chain reordering
•Creation and placement of memory macros
•Analog IP integration
•Power mesh creation and analysis
•Clock tree synthesis
•Routing
•Parasitic extraction
•Timing verification
•Timing improvements for critical macro blocks
•Timing closure
•Noise analysis
•IR drop analysis and power estimation as required
•LVS/DRC
•Implementation of ECO changes
• Equivalence checking – RTL to gates, and gates to gates
Candidate Qualification Requirements
Candidate must:
•Hold BSEE (MS preferred).
•Have minimum of 5 years hands-on experience in IC back-end physical design and verification.
•Project or team management skills including scheduling, resource management, and progress reporting
•Have at least 2 years using Magma place and route tool.
•Have completed hierarchical IC projects in 90 nm and below.
•Have the ability to independently identify and resolve design, tool, and flow problems
•Be able to design and implement physical design strategies and methodologies for deep submicron designs.
•Be able to complete block and chip level LVS and DRC
•Exhibit good written and verbal English skills and ability to work with internal and external design teams.
Any of the following is beneficial:
•STA constraint design
•Conversational in Mandarin dialect
If you are interested, please email with your resume: careers_us@availink.com
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