Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I guess, that 64-bit CLA adder is bad idea due to very complicated expressions for generate and propagate signals.
I would recommend to use eight 8-bit CLA adders with additional group propagate and generate signals as a building block for 64-bit adder.
Here is the example from @lter@ site:
ENTITY c_l_addr IS
x_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
carry_out : OUT STD_LOGIC
ARCHITECTURE behavioral OF c_l_addr IS
SIGNAL h_sum : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL carry_generate : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL carry_propagate : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL carry_in_internal : STD_LOGIC_VECTOR(7 DOWNTO 1);
h_sum <= x_in XOR y_in;
carry_generate <= x_in AND y_in;
carry_propagate <= x_in OR y_in;
carry_in_internal(1) <= carry_generate(0) OR (carry_propagate(0) AND carry_in);
inst: FOR i IN 1 TO 6 LOOP
carry_in_internal(i+1) <= carry_generate(i) OR (carry_propagate(i) AND carry_in_internal(i));
carry_out <= carry_generate(7) OR (carry_propagate(7) AND carry_in_internal(7));