xhdl is cheap and easy to use but it does not do good job when it comes to converting behavioral code or converting new constructs in verilog 2000 and beyond. Overall it converts about 80% of your code and you have to do the rest by hand.
i don't think it's a good idea to translate verilog & vhdl each other. if you have both model of them, try modlesim, ncsim or vcsmx to verification.
xhdl is good tool, but i still think that isn't good way.
you can read it into dc & write out with another format, but it's gtech_lib based.