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Looking for USB2.0 PHY IP

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visualart

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+umc +synopsys +usb core

Looking for USB2.0 PHY IP
I have some IP to exchange with u.
Tia
 

visualart

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Either is OK.
It is better verilog or schematics
 

CatKing

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no phy constructed by verilog, it's analog design!
 

maniasonic

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...but PHY should be an analog ( hence hard ) ip therefore it must be quite foundry dependent...
 

huxuefeng

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Please refers "www.opencores.com", U can find USB2.0 PHY IP.
 

visualart

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It is useless in the Opencore
 

mitchell

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I really want to find the USB2.0 transceiver , The
schematic and layout .
 

oasis

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as i know, usb phy is designed in the pad. and you could get some information from the ip providers, such as globleunichip in Taiwan.
 

ic_design

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Yes, PHY must be designed as an analog block, so must base on one process.
 

zyphor

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can you provide the information of your phy's successful foudry?
 

visualart

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who can provide the schemetic for us? Tia
 

bigrice

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visualart said:
It is useless in the Opencore

how do you say that?
I made it by using some src of Opencore's
 

visualart

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bigrice said:
visualart said:
It is useless in the Opencore

how do you say that?
I made it by using some src of Opencore's
I main that the free IP have many trap. and thank u , I got to the IP verified by silicon .
 

gold_kiss

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The USB 2.0 IP has a combination of Analog and Digital logic design blocks.
The basic analog blocks are Drivers and Pads. While the Digital logic is the USB Core.

You can get one using Synopsys Design Ware. Or for UMC, ISI, GlobalUnichip...etc.
ARC

Thanks,
Gold_kiss
 

iamchine

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Agree with Gold_kiss,the USB 2.0 PHY IP has a combination of Analog and Digital logic design blocks. While the basic analog blocks are not only Drivers and Pads but also Analog PLL for 480Mbps high speed transition.
So it depends on which foundry's process you select.You may ask the foundry for the ip or third-part ip provider.Then you can exchange IP with the provider.
 

visualart

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Thanks ,gold_kiss & iamchine.
I got to the USB 20 PHY IP verified by silicon .
I main what I shall provide if I design a analog IP. thank u .
 

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