Re: VHDL examples
-- examles of 74xx00
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY C00 IS
PORT( P1A, P1B, P2A, P2B, P3A, P3B,
P4A, P4B: IN std_logic:='U';
P1Y, P2Y, P3Y, P4Y: OUT std_logic);
end C00;
ARCHITECTURE behav OF C00 IS
begin
P1Y <= P1A nand P1B;
P2Y <= P2A nand P2B;
P3Y <= P3A nand P3B;
P4Y <= P4A nand P4B;
end behav;
Added after 2 minutes:
-- examles of 74xx245
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY C245 IS
PORT( GN, DIR: IN std_logic:='U';
A1, A2, A3, A4, A5, A6,
A7, A8, B1, B2, B3, B4,
B5, B6, B7, B8: INOUT std_logic);
end C245;
ARCHITECTURE behav OF C245 IS
begin
A1 <= B1 when (DIR='0' and GN='0') else 'Z';
A2 <= B2 when (DIR='0' and GN='0') else 'Z';
A3 <= B3 when (DIR='0' and GN='0') else 'Z';
A4 <= B4 when (DIR='0' and GN='0') else 'Z';
A5 <= B5 when (DIR='0' and GN='0') else 'Z';
A6 <= B6 when (DIR='0' and GN='0') else 'Z';
A7 <= B7 when (DIR='0' and GN='0') else 'Z';
A8 <= B8 when (DIR='0' and GN='0') else 'Z';
B1 <= A1 when (DIR='1' and GN='0') else 'Z';
B2 <= A2 when (DIR='1' and GN='0') else 'Z';
B3 <= A3 when (DIR='1' and GN='0') else 'Z';
B4 <= A4 when (DIR='1' and GN='0') else 'Z';
B5 <= A5 when (DIR='1' and GN='0') else 'Z';
B6 <= A6 when (DIR='1' and GN='0') else 'Z';
B7 <= A7 when (DIR='1' and GN='0') else 'Z';
B8 <= A8 when (DIR='1' and GN='0') else 'Z';
end behav;