money_kandan2004
Member level 3
hai,
i need this papers for my research work.
1. Macpherson, K., Stirling, I., Rice, G., Garcia-Alis, D., and Stewart,
R.:‘Arithmetic implementation techniques and methodologies for
3G uplink reception in Xilinx FPGAs’. Third Int. Conf. on 3G
Mobile Communication Technologies, 2002, (IEE Conf. Publ. no.
489), May 2002, pp. 191–195
2. Bull, D.R., and Horrocks, D.H.: ‘Primitive operator digital
filters’, IEE Proc. G, Circuits Devices Syst., 1991, 138, (3),
pp. 401–412
3.Meyer-Baese, U.: ‘Digital signal processing with field programmable
gate arrays’ (Springer-Verlag, Berlin, Heidelberg, 2001)
4. Gustafsson, O., and Wanhammar, L.: ‘ILP modelling of the common
subexpression sharing problem’. 9th Int. Conf. on Electronics, Circuits
and Systems, 2002, vol. 3, pp. 1171–1174
5. Jang, Y., and Yang, S.: ‘Low-power CSD linear phase FIR filter
structure using vertical common sub-expression’, Electron. Lett.,
2002, 38, (15), pp. 777–779
6. Dempster, A.G., and Macleod, M.D.: ‘Constant integer multiplication
using minimum adders’, IEE Proc., Circuits Devices Syst., 1994, 141,
(5), pp. 407–413
7. Wirthlin, M.J., and McMurtrey, B.: ‘Efficient constant coefficient
multiplication using advanced FPGA architectures’. Proc. 11th Int.
Workshop on Field-Programmable Logic and Applications, 2001,
pp. 555–564
8. Xilinx Inc.: ‘Distributed arithmetic FIR filter v8.0’, http://www.xilinx.com
9. Synplicity Inc., http://www.synplicity.com
i need this papers for my research work.
1. Macpherson, K., Stirling, I., Rice, G., Garcia-Alis, D., and Stewart,
R.:‘Arithmetic implementation techniques and methodologies for
3G uplink reception in Xilinx FPGAs’. Third Int. Conf. on 3G
Mobile Communication Technologies, 2002, (IEE Conf. Publ. no.
489), May 2002, pp. 191–195
2. Bull, D.R., and Horrocks, D.H.: ‘Primitive operator digital
filters’, IEE Proc. G, Circuits Devices Syst., 1991, 138, (3),
pp. 401–412
3.Meyer-Baese, U.: ‘Digital signal processing with field programmable
gate arrays’ (Springer-Verlag, Berlin, Heidelberg, 2001)
4. Gustafsson, O., and Wanhammar, L.: ‘ILP modelling of the common
subexpression sharing problem’. 9th Int. Conf. on Electronics, Circuits
and Systems, 2002, vol. 3, pp. 1171–1174
5. Jang, Y., and Yang, S.: ‘Low-power CSD linear phase FIR filter
structure using vertical common sub-expression’, Electron. Lett.,
2002, 38, (15), pp. 777–779
6. Dempster, A.G., and Macleod, M.D.: ‘Constant integer multiplication
using minimum adders’, IEE Proc., Circuits Devices Syst., 1994, 141,
(5), pp. 407–413
7. Wirthlin, M.J., and McMurtrey, B.: ‘Efficient constant coefficient
multiplication using advanced FPGA architectures’. Proc. 11th Int.
Workshop on Field-Programmable Logic and Applications, 2001,
pp. 555–564
8. Xilinx Inc.: ‘Distributed arithmetic FIR filter v8.0’, http://www.xilinx.com
9. Synplicity Inc., http://www.synplicity.com
