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Looking for papers about power management in SoC

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airace

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power management:Req

Can someone post up some good info on Power management in SoCs

Thanks in adv, :)
 

A basic rules for any analog design is to have a power down mode for ALL cells. At least it save some DC power.

OkGuy?
 

Change the sytem clock frequency during
power-down mode & aggressive gated-clock design isn't a bad idea.

Hope it helps :)
 

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