Looking for information about EDK system.ucf

[HUYCUONGBK]

in system.ucf have many things such as :


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NET sys_clk TNM_NET = "sys_clk";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;


TIMESPEC "TSCPU" = PERIOD "cpu_clk" 2.998 ns HIGH 50 %;

NET sys_clk LOC = B13;
NET sys_clk IOSTANDARD = LVCMOS33;


inst "clocks_0/clocks_0/dcm3" LOC = DCM_X1Y0;
#inst "clocks_0/clocks_0/dcm4" LOC = DCM_X1Y1;

#inst "clocks_0/clocks_0/clk_bufg" LOC = BUFGMUX7P;
#inst "clocks_0/clocks_0/clkcpu_bufg" LOC = BUFGMUX6S;

NET PP_DIR TIG;
NET PP_DIR SLEW = SLOW;
NET PP_DIR DRIVE = 2;

NET fpga_led<0> LOC = G6; # PMC_CONN4_IO24 (TOP_YELLOW_LED_15) - MSB
NET fpga_led<1> LOC = L7; # PMC_CONN4_IO23 (TOP_YELLOW_LED_14)
NET fpga_led<2> LOC = G5; # PMC_CONN4_IO22 (TOP_YELLOW_LED_13)
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And more more.........I can't understand them . You can tell me mean of them . And when we use for our design.

If you have file.pdf about it , please send me. Thank you
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[echo47]

EDK system.ucf

Those are timing constraints, primitive placement locations, pin locations, I/O driver configuration, and other FPGA design details.
See your Xilinx ISE "Constraints Guide" (cgd.pdf). It's one of the many PDF manuals installed with ISE.

Welcome to the wild world of FPGA design.