vino_2007ece@yahoo.co.in
Newbie level 3
E.VINOTH
vino_2007ece@yahoo.co.in
Mobile No: +91-8012239301.
OBJECTIVE:
Associate with a progressive organization that gives me the scope to apply my knowledge and skills in the Area of VHDL, Verilog-HDL, TCL, PSL and Lab Windows-CVI, FPGA/ASIC, Synthesis and implementation to involve as a part of the team that dynamically works towards the growth of the organization.
SUMMARY:
• 3+ years of Experience in FPGA design (RTL), FPGA Verification and Validation Field.
• Having professional experience using VHDL, VERILOG_HDL, TCL, C, FPGA/ASIC, LabWindows-CVI and VB.
• Actively involved Various Project Phases: Design, Program Specification, Test Bench development, Synthesis, implementation, source code verification and validation, writing PSL properties, code coverage and functional coverage, lint rules analysis.
• Worked with Latest Software tools Riviera pro, Xilinx, Libero, Active HDL, ModelSim and ORCAD.
• Lead the verification effort for generating test benches using vhdl ,verilog
• Experience in Synthesis and implementation for FPGA.
• Strong Knowledge in VHDL, C, VERILOG_HDL, TCL.
PROFESSIONAL EXPERIENCE:
• Working as Research Scientist in the field of FPGA in SAMEER–Centre for Electromagnetics, R&D (Government of India), Chennai India.
• Worked as FPGA Design , Verification and Validation Engineer
(Contract) in Vikram Sarabhai Space Centre (ISRO), Kerala
Thiruvananthapuram, India.
• Worked as Graduate Trainee in the field of FPGA in (VSSC)
Vikram Sarabhai Space Centre (ISRO), Thiruvananthapuram, India.
EDUCATION & CREDENTIALS:
Bachelor of Engineering in Electronics and Communication at Adhiparasakthi College of Engineering College, kalavai (Vellore). Mark Secured-74% First class.
Intermediate (10+2) in Bio-Maths at M.K.V.Hr Secondary School. Arani (Thiruvallore). Mark Secured-81% First class.
S.S.L.C (10th) in General at M.K.V.Hr Secondary School, Arani (Thiruvallore).
Mark Secured-79% First class.
PROFESSIONAL SKILLS:
Languages : VHDL, VERILOG_HDL, PCL, C, VB.
Operating System : MS DOS, windows (2007 and XP).
Scripting language : TCL
Software EDA tools : ACTEL-LIBERO-IDE, ORCAD, Model Sim,
Rivira-Pro, Xilinx-ISE, Active_HDL
Hardware Exposure : Xilinx FPGAs: Spartan 3 AN.
Tool exposure : Synopsys
Verification Environment: Module level
Functional coverage : Code coverage & Assertion (PSL).
Technical Skills : RTL Design and FPGA Synthesis, Test Bench
Development, FPGA Design Flow, Digital Design
Synthesize using Xilinx ISE, State Machine Design,
Code coverage and functional coverage.
PROJECT DETAILS:
1. RLV_TD (reusable launch vehicles test device) Flush Air data system, India
Environment : Synthesis Xilinx, Simulation modelsim, Active HDL
Functionality : Compute the air data parameter in real time.
Role : Design RTL code and verification.
Team Size : 3
Company : VSSC, ISRO.
Description:
This project is designed for use in RLV to compute the air data parameter like Mach number, angle of attack and sideslip, dynamic pressure etc, the air data parameter are computed from the pressure information acquired from the pressure sensors located in the pressure orifices situated on the nose cone of RLV And FADS (Flush air data system) – electronics package module to carry out the task of computation air parameters in real time.
Responsibility
• Implementing in Synthesizable RTL code.
• Developed Synthesizable Test Bench.
• RTL coding to apply the stimuli and compare the results.
• Used LINT rules analysis to avoid the violation which is occurred in source code.
• Written PSL properties for checking the functionality of the I/O pins.
• Carried out code coverage, Branch coverage, statement coverage using macro command.
• Developed run macro (TCL) command (.do) for simulation and synthesis.
2. Moon Impact Probe (MIP), India
Environment : Riviera Pro 2007, Active HDL
Role : Design RTL code and verification &validation.
Team Size : 3
Company : VSSC, ISRO.
Description:
The MIP sequencer FPGA consists of three sub module namely clock buffer, clock divider & counter. In this project, command signal is activated when the sending of data values in the clock buffer circuit 1 MHZ clock is buffered & the o/p is fed to the clock divider circuit which is used to divide the 1microsecond clock into 1440microsecond clock. In the counter, the 8 bit data is entered at particular time intervals such that each data are placed at corresponding address location by the address counter.
Responsibility
• Implementing in Synthesizable RTL code.
• Conduct and participate in design and code reviews
• Developed test bench to verify function of the Moon Impact probe (MIP).
• Carried out code coverage, Branch coverage, statement coverage.
• Written PSL properties for checking the functionality of the I/O pins.
• Diagnose and debug RTL related problems.
3. Compact solid state C-band Transponder, India
Environment : Synthesis Xilinx, Simulation modelsim 5.5.
Role : Implementing RTL code.
Team Size : 2
Company : VSSC, ISRO.
Description:
The main objective of this project to transmit & receive the data at particular frequencies. This project consists of transmitter, receiver & interface circuit. The receiver accepts the interrogating signal from radar & generates the detected pulse, on pulse to pulse basic which is then delayed & retransmitted at different frequency.
Responsibility
• According to the Specification, Created Test plan for Compact solid state C-band Transponder.
• Developed Test bench for verify the function of the design.
• Test & Debugged the COST Core.
• Developed Macro run command (TCL) for simulation, synthesis & implementation.
• Prepare and maintain product documentation, including specifications and design documentation
4. MLC (MULTI LEAF COLLIMATOR)
Environment : Synthesis Xilinx, Simulation modelsim 5.5
Role : Implementing RTL code and verification.
Team Size : 2
Company : SAMEER-CEM, INDIA
Description:
The MLC is used for treating the tumor of cancer patients (Radiation Therapy).The TPS is to control the MLC hardware to bring the shape of tumors in the MLC for effective treatment. The treatment is automated through TPS.The MLC has 2 banks of leaves (tungsten alloy) for passing the radiation to the affected tissues. The MLC is to allow the radiation beam in the shape of the tumor which is planned by TPS.The movement of the leaves is controlled by individual stepper motors.
Responsibility
• Implementing in Synthesizable RTL code.
• Write and analyze test plans, conduct design tests and evaluate test results.
• Diagnose and debug RTL related problems.
• RTL coding to apply the stimuli and compare the results.
• Used LINT rules analysis to avoid the violation which is occurred in source code
• Conduct and participate in design and code reviews
• Prepare and maintain product documentation, including specifications and design documentation
Strong logic design skills;
• RTL code design with VHDL.
• Experience synthesizing and implementing designs in hardware.
• Knowledge of test bench coding.
• Knowledge of Xilinx Synthesis Tool.
• Knowledge of Xilinx Spartan 3 AN FPGA.
• Knowledge of developing TCL macro run (.do) command.
• Knowledge in FPGA/ASIC design.
• Experience on handling multimillion gate FPGA Designs.
• Experience in VHDL/ Verilog RTL Coding.
• Experience VHDL/ Verilog based test bench development.
• Experience in Synthesis and implementation for FPGA.
Methods for Verification:
• Understanding the existing project fully and thoroughly
• Use LINT rules analysis to avoid errors which is occurred in source code
• Verify the top module source code by writing test bench.
• Developing run (.do) macro command for simulation and synthesis.
• write PSL (properties specification language) properties to verify the source
Code at different condition and carryout the cover ages.
• Use logical operators such as Next, after, before, until, stable, never,
Always, eventually, condition.
• Carry out code coverage, Branch coverage, statement coverage,
Toggle coverage & functional coverage data.
VHDL & VERILOG PROJECT:
8259 programmable interrupt controller,
8254 timer/counter,
SECDED (single bit error Corrections and double bit detection)
Traffic light controller.
COST(compact solid state C band Transponder)
MIP (MOON IMPACT PROBE)
ACADEMIC PROJECT (Graduate):
TITLE : “HYBRID ANTI BALLISTIC MISSILE.”
LANGUAGE : MICRO “C”.
This project is developed for the launching of anti ballistic missile which is surface to surface launching missile. The missile being developed is a self intelligent device which means if opponent missile enter the frontier then the antiballistic missile will attack that opponent missile at fixed position before attack itself to determine the angle &distance of the opponent missile.
EXTRA CURRICULAR ACTIVITIES:
1. Completed PGDCA Course
2. Implant Training in ALL INDIA RADIO in Chennai.
3. Qualified in GATE 2010.
PERSONAL DETAILS:
Marital Status : Single
Nationality : Indian
Permanent Address : 97, New Tamil colony,
Arani &post, Ponneri (T.k),
(District), Tamilnadu. Pin - 601101.
Mobile : +91-8012239301.
DECLARATION
I hereby declare that the above written particulars are true to the best of my knowledge and belief.
Date:
Place:
Yours Sincerely,
E.VINOTH
vino_2007ece@yahoo.co.in
Mobile No: +91-8012239301.
OBJECTIVE:
Associate with a progressive organization that gives me the scope to apply my knowledge and skills in the Area of VHDL, Verilog-HDL, TCL, PSL and Lab Windows-CVI, FPGA/ASIC, Synthesis and implementation to involve as a part of the team that dynamically works towards the growth of the organization.
SUMMARY:
• 3+ years of Experience in FPGA design (RTL), FPGA Verification and Validation Field.
• Having professional experience using VHDL, VERILOG_HDL, TCL, C, FPGA/ASIC, LabWindows-CVI and VB.
• Actively involved Various Project Phases: Design, Program Specification, Test Bench development, Synthesis, implementation, source code verification and validation, writing PSL properties, code coverage and functional coverage, lint rules analysis.
• Worked with Latest Software tools Riviera pro, Xilinx, Libero, Active HDL, ModelSim and ORCAD.
• Lead the verification effort for generating test benches using vhdl ,verilog
• Experience in Synthesis and implementation for FPGA.
• Strong Knowledge in VHDL, C, VERILOG_HDL, TCL.
PROFESSIONAL EXPERIENCE:
• Working as Research Scientist in the field of FPGA in SAMEER–Centre for Electromagnetics, R&D (Government of India), Chennai India.
• Worked as FPGA Design , Verification and Validation Engineer
(Contract) in Vikram Sarabhai Space Centre (ISRO), Kerala
Thiruvananthapuram, India.
• Worked as Graduate Trainee in the field of FPGA in (VSSC)
Vikram Sarabhai Space Centre (ISRO), Thiruvananthapuram, India.
EDUCATION & CREDENTIALS:
Bachelor of Engineering in Electronics and Communication at Adhiparasakthi College of Engineering College, kalavai (Vellore). Mark Secured-74% First class.
Intermediate (10+2) in Bio-Maths at M.K.V.Hr Secondary School. Arani (Thiruvallore). Mark Secured-81% First class.
S.S.L.C (10th) in General at M.K.V.Hr Secondary School, Arani (Thiruvallore).
Mark Secured-79% First class.
PROFESSIONAL SKILLS:
Languages : VHDL, VERILOG_HDL, PCL, C, VB.
Operating System : MS DOS, windows (2007 and XP).
Scripting language : TCL
Software EDA tools : ACTEL-LIBERO-IDE, ORCAD, Model Sim,
Rivira-Pro, Xilinx-ISE, Active_HDL
Hardware Exposure : Xilinx FPGAs: Spartan 3 AN.
Tool exposure : Synopsys
Verification Environment: Module level
Functional coverage : Code coverage & Assertion (PSL).
Technical Skills : RTL Design and FPGA Synthesis, Test Bench
Development, FPGA Design Flow, Digital Design
Synthesize using Xilinx ISE, State Machine Design,
Code coverage and functional coverage.
PROJECT DETAILS:
1. RLV_TD (reusable launch vehicles test device) Flush Air data system, India
Environment : Synthesis Xilinx, Simulation modelsim, Active HDL
Functionality : Compute the air data parameter in real time.
Role : Design RTL code and verification.
Team Size : 3
Company : VSSC, ISRO.
Description:
This project is designed for use in RLV to compute the air data parameter like Mach number, angle of attack and sideslip, dynamic pressure etc, the air data parameter are computed from the pressure information acquired from the pressure sensors located in the pressure orifices situated on the nose cone of RLV And FADS (Flush air data system) – electronics package module to carry out the task of computation air parameters in real time.
Responsibility
• Implementing in Synthesizable RTL code.
• Developed Synthesizable Test Bench.
• RTL coding to apply the stimuli and compare the results.
• Used LINT rules analysis to avoid the violation which is occurred in source code.
• Written PSL properties for checking the functionality of the I/O pins.
• Carried out code coverage, Branch coverage, statement coverage using macro command.
• Developed run macro (TCL) command (.do) for simulation and synthesis.
2. Moon Impact Probe (MIP), India
Environment : Riviera Pro 2007, Active HDL
Role : Design RTL code and verification &validation.
Team Size : 3
Company : VSSC, ISRO.
Description:
The MIP sequencer FPGA consists of three sub module namely clock buffer, clock divider & counter. In this project, command signal is activated when the sending of data values in the clock buffer circuit 1 MHZ clock is buffered & the o/p is fed to the clock divider circuit which is used to divide the 1microsecond clock into 1440microsecond clock. In the counter, the 8 bit data is entered at particular time intervals such that each data are placed at corresponding address location by the address counter.
Responsibility
• Implementing in Synthesizable RTL code.
• Conduct and participate in design and code reviews
• Developed test bench to verify function of the Moon Impact probe (MIP).
• Carried out code coverage, Branch coverage, statement coverage.
• Written PSL properties for checking the functionality of the I/O pins.
• Diagnose and debug RTL related problems.
3. Compact solid state C-band Transponder, India
Environment : Synthesis Xilinx, Simulation modelsim 5.5.
Role : Implementing RTL code.
Team Size : 2
Company : VSSC, ISRO.
Description:
The main objective of this project to transmit & receive the data at particular frequencies. This project consists of transmitter, receiver & interface circuit. The receiver accepts the interrogating signal from radar & generates the detected pulse, on pulse to pulse basic which is then delayed & retransmitted at different frequency.
Responsibility
• According to the Specification, Created Test plan for Compact solid state C-band Transponder.
• Developed Test bench for verify the function of the design.
• Test & Debugged the COST Core.
• Developed Macro run command (TCL) for simulation, synthesis & implementation.
• Prepare and maintain product documentation, including specifications and design documentation
4. MLC (MULTI LEAF COLLIMATOR)
Environment : Synthesis Xilinx, Simulation modelsim 5.5
Role : Implementing RTL code and verification.
Team Size : 2
Company : SAMEER-CEM, INDIA
Description:
The MLC is used for treating the tumor of cancer patients (Radiation Therapy).The TPS is to control the MLC hardware to bring the shape of tumors in the MLC for effective treatment. The treatment is automated through TPS.The MLC has 2 banks of leaves (tungsten alloy) for passing the radiation to the affected tissues. The MLC is to allow the radiation beam in the shape of the tumor which is planned by TPS.The movement of the leaves is controlled by individual stepper motors.
Responsibility
• Implementing in Synthesizable RTL code.
• Write and analyze test plans, conduct design tests and evaluate test results.
• Diagnose and debug RTL related problems.
• RTL coding to apply the stimuli and compare the results.
• Used LINT rules analysis to avoid the violation which is occurred in source code
• Conduct and participate in design and code reviews
• Prepare and maintain product documentation, including specifications and design documentation
Strong logic design skills;
• RTL code design with VHDL.
• Experience synthesizing and implementing designs in hardware.
• Knowledge of test bench coding.
• Knowledge of Xilinx Synthesis Tool.
• Knowledge of Xilinx Spartan 3 AN FPGA.
• Knowledge of developing TCL macro run (.do) command.
• Knowledge in FPGA/ASIC design.
• Experience on handling multimillion gate FPGA Designs.
• Experience in VHDL/ Verilog RTL Coding.
• Experience VHDL/ Verilog based test bench development.
• Experience in Synthesis and implementation for FPGA.
Methods for Verification:
• Understanding the existing project fully and thoroughly
• Use LINT rules analysis to avoid errors which is occurred in source code
• Verify the top module source code by writing test bench.
• Developing run (.do) macro command for simulation and synthesis.
• write PSL (properties specification language) properties to verify the source
Code at different condition and carryout the cover ages.
• Use logical operators such as Next, after, before, until, stable, never,
Always, eventually, condition.
• Carry out code coverage, Branch coverage, statement coverage,
Toggle coverage & functional coverage data.
VHDL & VERILOG PROJECT:
8259 programmable interrupt controller,
8254 timer/counter,
SECDED (single bit error Corrections and double bit detection)
Traffic light controller.
COST(compact solid state C band Transponder)
MIP (MOON IMPACT PROBE)
ACADEMIC PROJECT (Graduate):
TITLE : “HYBRID ANTI BALLISTIC MISSILE.”
LANGUAGE : MICRO “C”.
This project is developed for the launching of anti ballistic missile which is surface to surface launching missile. The missile being developed is a self intelligent device which means if opponent missile enter the frontier then the antiballistic missile will attack that opponent missile at fixed position before attack itself to determine the angle &distance of the opponent missile.
EXTRA CURRICULAR ACTIVITIES:
1. Completed PGDCA Course
2. Implant Training in ALL INDIA RADIO in Chennai.
3. Qualified in GATE 2010.
PERSONAL DETAILS:
Marital Status : Single
Nationality : Indian
Permanent Address : 97, New Tamil colony,
Arani &post, Ponneri (T.k),
(District), Tamilnadu. Pin - 601101.
Mobile : +91-8012239301.
DECLARATION
I hereby declare that the above written particulars are true to the best of my knowledge and belief.
Date:
Place:
Yours Sincerely,
E.VINOTH
