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Looking for fifo build by fpga

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somayeh

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building fifo by fpga

Hi people,

Could anybody go forward and build something?
Any interesting to share ??

Regards,
 

EDALIST

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Re: building fifo by fpga

what is the problem ?

you can use xilinx coregen to generate fifo.

if you want to generate your own fifo, just use a DPRAM, with your own address counters, and control signals.[/i]
 

it_boy

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Re: building fifo by fpga

these documents might be useful if you are planning to design a fifo yourself

hxxp://www.geocities.com/deepakgeorge2000/vlsi_book/Asynch1.pdf
hxxp://www.geocities.com/deepakgeorge2000/vlsi_book/async_fifo2.pdf
 

    somayeh

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vishwa

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Re: building fifo by fpga

You can easily build it. Try


Generate a set of registers and shift/rotate the data side by side for each clock cycle.
 

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