mvvijay78
Member level 4
ic design power planning
Hi,
We are working on the standard cell based digital IC design.Does anyone have good documents that would help in better power palnning.
Following are my main doubts:
1)Using a power analysis tool we can estimate the power consumed by that block but my concern is the power reported after CTS will alwys be much higher than that reported before CTS?So how do i go about it?
2)Suppose for the IC i decide to build a power ring for the core(assume that the block consumes 350mW of power) and i am targetting 6 metal layer 0.18u TSMC library.How do i caluculte the power ring widths.
3)Also how do i build the power structure for the IO pads?
Regards
Vicky
Hi,
We are working on the standard cell based digital IC design.Does anyone have good documents that would help in better power palnning.
Following are my main doubts:
1)Using a power analysis tool we can estimate the power consumed by that block but my concern is the power reported after CTS will alwys be much higher than that reported before CTS?So how do i go about it?
2)Suppose for the IC i decide to build a power ring for the core(assume that the block consumes 350mW of power) and i am targetting 6 metal layer 0.18u TSMC library.How do i caluculte the power ring widths.
3)Also how do i build the power structure for the IO pads?
Regards
Vicky