hi,
i think different process has different techfile,so you can not use any other techfiles except the one your foundry provided. so you can ask your foundry for help.
good luck
jeff
I am quite doubtful about your post, DRC techfile ? seems to be new to me ,as there are no seperate techfiles for DRC/LVS...in fact there are no techfiles at all.
Techfiles are used as an input to the tool say Virtuso/ Laker which is used for making layout/ writing out or readin GDS.(as per the technology)
However, techfiles may have a DRC/LVS section, are you talking about the sections only ?
you can search on your computer with name 'divaDRC.rul' (use diva check)
You also download lib NCSU on 'www.cadence.ncsu.edu'. This lib support many technology which presented in MOSIS (www.mosis.com). This lib have enough techfile for you to check DRC, LVS...
About NMOS and PMOS model, there are many model so I don't know which model you need. You can use Bsim 3 model (Cadence support this model)
Hope it useful