Looking for a Verilog source code editor with certain features

[free_electron]

I found some other threads here but they don't provide an answer. so : First things first : i'm not atlking about synthesizers / simulators but just plain source code editors.

what i am looking for in a verilog editor ( also vhdl )
1) - autocompletion Visual studio style.

reg [15:0] my_registername;

if i type 'my_' there should already be a pulldownlist hovering so i can quickly pick the name i want, then hit <tab> and it completes the sentence.
Same for keywords like posedge, negedge , begin , endcase etc etc etc
I found editors that can pick up the keywords (notepad++) but not the stuff you define in the code itself.

2) radix conversion
if i write:

    my_registername <=16'd2;

i want to be able to right-click the 16'd2 and select thing like : convert to binary , convert to hex or convert to decimal.
convert to binary would do this:

    my_registername <=16'd2;  // after clicking becomes :
    my_registername <=16'b0000_0000_0000_0010;

this would make so that if you need to flip a bit , you can swap to binary , edit the one bit and flip back to hex or decimal.

3) expansion/reduction

my_registername <= 4;

i right click the 4 and say : convert to hex ( 4 is assumed as decimal since there is no 'header'
it would go and look up the siz of my_registername ( beeing 15:0 ) and 'beautify the code from

or even better : assign those conversion functions to F9 F10 F11 or some other function key. the cursor is on it : bam. converted , expanded and cleaned up.

 my_registername <= 4;
 my_registername <= 16'h0004;

similar if i wrote

 my_registername <= hff;

and selected decimal
it would have 'beautified' to

 my_registername <= 16'd255;

if i resize an array (tyically a reg or wire array) there should be a search and replace that scans for all assignments to the array and checks for misalignments. ( like warning when too much stuff is beeing crammed into the register if is shrunk the register , or if not enough is in. a listbox would be nice so i can simple doubleclick the line and fix it. similar to what studio.net 2005 has.
you immediately see the problems double click them , editor jumps there and you fix them.

4)automatic code cleanup

a code snippet

  if (a)   q <=7;
  else  q<=9;

while making the logic i suddenly realise that if a is true i also need an additional condition

so i type

  if (a)   q <=7;
         p = 1;         
  else  q<=9;

the moment i hit return after 'p=1;' the editor should detect that there is now more then one statement between if and else and a begin-end block is in order and thus inject it .

if (a)  begin
   q <=7;
   p = 1;         
end
else  q<=9;

5) and then tons of other cleanup things like missing semicolons , commas in input/output lists etcetera.

my frustration is that , everytime i want to compile a block of logic i first have to sift through tons of typos and things like missing semicolons.
there should also be a realtime warning if you access a variable or wire that is not defined. you can of course use 'default nettype = none. but then you leave that to the compiler. compiler time is precious. the compiler sometimes runs for 10 to 15 minutes and then suddenly bombs out because of a missing semicolon somewhere ... aaarrgh. And when it compiles you have 500 warnings about size misalignments... and you can go back and clean those up as well... ( we have strict coding policies where i work : it is not allowd to let the synthesizer expand stuff. So you can not do this :
my_register <=0; If 'my_register' is 37 bits you need to write explicitly 37'd0;

Its almost 2008. So about time verilog / vhdl coders get some decent editors that programmers have enjoyed for years.

so : who knows about any editor that is capable of such features ?

 

[gliss]

verilog pretty printer

I think you'll find some of these features you describe as obvious advantages may not be welcome by all HDL coders.
That being said, you might want to try the Verilog or VHDL plugins for the Eclipse development system.

More information here: **broken link removed**


Screen shot:


**broken link removed**

 

[ds18s20]

vedit eclipse verilog

IMHO Eclipse is a horrible java-based piece of software, just like all the other java stuff (they still teach java you know) that academia is pushing. I find it totally useless and could not stand finishing the class to never touch java again.

Bottom line - Eclipse response is typical for any hava software - slow as hell, under-water-scuba feeling. far from "real" application user response.

just my 2 cents of course...

I use Programmer's Notepad **broken link removed**

 

[free_electron]

verilog code editor

sorry , both of em do not do what i want.

i tried the vedit plugin for eclipse: i get finger cramps from hitting ctrl-space all the time. I'm after visual studio style. as you type the listbox hovers. hit tab and it plugs. Right now i'm evaluating lickedit. that seems to do this correctly.

the only problem with slickedit is that 'find definition' for verilog wires or registers doesn't work. grrrr.

As far as programmers notepad goes ; that's VHDL not Verilog ! different synax.

Still leaves the things like base conversion and especially autosizing variables ! i want the tool to go and find the definition of a register and plug the correct size.

If i change the size of a register i want to see warnings where a mismatch now exists ! ( it should not touch the code in this instance : just show me a list where problems exist, so i can correct them )

my problems are the following : i am using very large registers ( 128 and 256 bits ... per default a zero gets expanded to .. 32 bits ! so if you have this :

reg [127:0] my_reg;
my_reg <=0 ;

this goes horribly wrong as the synth expands the zero to 32 bit per default ... luckily it barfs. but that is wasted synth time. ( the project i am working on now takes over half an hour to synthetise. very funny if it barfs after 20 minutes because of a 'typo' ....

I also want a pretty-printer function. its there somehwere in slickedit. just havent found it yet ...